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10-Bit, 4x Oversampling SDTV Video Decoder ADV7180
FEATURES
Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4x oversampling for CVBS, 2x oversampling for Y/C mode, and 2x oversampling for YPrPb (per channel) Three video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-video), and YPrPb (component) video input support 5-line adaptive comb filters and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLTTM), signal processing, and enhanced FIFO management give mini-TBC functionality Integrated AGC with adaptive peak white mode Macrovision(R) copy protection detection NTSC/PAL/SECAM autodetection 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, FIELD1 1.0 V analog input signal range Four general-purpose outputs (GPO)2 Full feature VBI data slicer with teletext support (WST) Power-down mode and ultralow sleep mode current 2-wire serial MPU interface (I2C(R) compatible) 1.8 V analog, 1.8 V PLL, 1.8 V digital, 3.3 V I/O supply -40C to +85C temperature grade Two package types: 40-lead, 6 mm x 6 mm, Pb-free LFCSP 64-lead, 10 mm x 10 mm, Pb-free LQFP
APPLICATIONS
Digital camcorders and PDAs Low-cost SDTV PIP decoder for digital TVs Multichannel DVRs for video security AV receivers and video transcoding PCI-/USB-based video capture and TV tuner cards Personal media players and recorders Smartphone/multimedia handsets In-car/automotive infotainment units Rearview camera/vehicle safety systems
FUNCTIONAL BLOCK DIAGRAM
XTAL1 XTAL ANALOG VIDEO INPUTS AIN1 AIN2 AIN3 AIN41 AIN51 AIN61 CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC
FIFO
MUX BLOCK
OUTPUT BLOCK
AA FILTER AA FILTER AA FILTER
10-BIT, 86MHz ADC
DIGITAL PROCESSING BLOCK 2D COMB
8-BIT/161-BIT PIXEL DATA P7 TO P0 VS HS FIELD2 GPO1 SFL INTRQ
SHA
A/D
VBI SLICER COLOR DEMOD
REFERENCE
I2C/CONTROL
ADV7180
05700-001
SCLK SDATA ALSB RESET PWRDWN
1ONLY AVAILABLE ON 64-LEAD PACKAGE. 240-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.
Figure 1.
GENERAL DESCRIPTION
The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component video data compatible with the 8-bit ITU-R BT.656 interface standard. The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7179. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs, if required The accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. Three analog video input channels accept standard composite, S-video, or component video signals, supporting a wide range of consumer video sources.
1 2
AGC and clamp-restore circuitry allow an input video signal peak-to-peak range up to 1.0 V. Alternatively, these can be bypassed for manual settings. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with 5% line length variation. Output control signals allow glueless interface connections in many applications. The ADV7180 is programmed via a 2-wire, serial, bidirectional port (I2C compatible). The ADV7180 is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. A chip-scale, 40-lead, Pb-free LFCSP package option makes the decoder ideal for spaceconstrained portable applications. A 64-lead LQFP package is also available (pin compatible with ADV7181B).
The ADV7180 LFCSP-40 uses one pin to output VS or FIELD. ADV7180 LQFP-64 only.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADV7180 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Comparison with the ADV7181B .............................................. 5 Functional Block Diagrams............................................................. 6 Specifications..................................................................................... 7 Electrical Characteristics............................................................. 7 Video Specifications..................................................................... 8 Timing Specifications .................................................................. 9 Analog Specifications................................................................... 9 Thermal Specifications ................................................................ 9 Timing Diagrams........................................................................ 10 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 40-Lead LFCSP ........................................................................... 12 64-Lead LQFP ............................................................................. 13 Analog Front End ........................................................................... 15 Input Configuration ................................................................... 16 INSEL[3:0], Input Selection, Address 0x00 [3:0] ................... 16 Analog Input Muxing ................................................................ 17 Antialiasing Filters ..................................................................... 18 Global Control Registers ............................................................... 19 Power-Saving Modes.................................................................. 19 Reset Control .............................................................................. 19 Global Pin Control ..................................................................... 19 Global Status Register .................................................................... 21 Identification............................................................................... 21 Status 1 ......................................................................................... 21 Autodetection Result.................................................................. 21 Status 2 ......................................................................................... 21 Status 3 ......................................................................................... 21 Video Processor .............................................................................. 22 SD Luma Path ............................................................................. 22 SD Chroma Path......................................................................... 22 Sync Processing .......................................................................... 23 VBI Data Recovery..................................................................... 23 General Setup.............................................................................. 23 Color Controls ............................................................................ 25 Clamp Operation........................................................................ 27 Luma Filter .................................................................................. 28 Chroma Filter.............................................................................. 31 Gain Operation........................................................................... 32 Chroma Transient Improvement (CTI) .................................. 36 Digital Noise Reduction (DNR) and Luma Peaking Filter... 37 Comb Filters................................................................................ 38 IF Filter Compensation ............................................................. 40 AV Code Insertion and Controls ............................................. 41 Synchronization Output Signals............................................... 43 Sync Processing .......................................................................... 50 VBI Data Decode ....................................................................... 50 I2C Readback Registers .............................................................. 59 Pixel Port Configuration ............................................................... 72 GPO Control ................................................................................... 73 MPU Port Description................................................................... 74 Register Access............................................................................ 75 Register Programming............................................................... 75 I2C Sequencer.............................................................................. 75 I2C Register Maps ........................................................................... 76 I2C Programming Examples........................................................ 106 ADV7180 LQFP-64.................................................................. 106 ADV7180 LFCSP-40 ................................................................ 107 PCB Layout Recommendations.................................................. 108 Analog Interface Inputs ........................................................... 108 Power Supply Decoupling ....................................................... 108 PLL ............................................................................................. 108 VREFN and VREFP................................................................. 108 Digital Outputs (Both Data and Clocks) .............................. 108 Digital Inputs ............................................................................ 108 Typical Circuit Connection......................................................... 109 Outline Dimensions ..................................................................... 111 Ordering Guide ........................................................................ 111
Rev. A | Page 2 of 112
ADV7180
REVISION HISTORY
11/06--Rev. 0 to Rev. A Changes to Table 10 and Table 11 .................................................16 Changes to Table 30 ........................................................................28 Changes to Gain Operation Section .............................................33 Changes to Table 43 ........................................................................35 Changes to Table 97 ........................................................................72 Changes to Table 99 ........................................................................73 Changes to Table 103 ......................................................................80 Changes to Figure 54 ....................................................................110 1/06--Revision 0: Initial Version
Rev. A | Page 3 of 112
ADV7180 INTRODUCTION
The ADV7180 is a versatile one-chip multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format. The simple digital output interface connects gluelessly to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devides digital video encoders, such as the ADV7179. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs that do not support the ITU-R BT.656 interface standard.
STANDARD DEFINITION PROCESSOR
The ADV7180 is capable of decoding a large selection of baseband video signals in composite, S-video, and component formats. The video standards supported by the video processor include PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can automatically detect the video standard and process it accordingly. The ADV7180 has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available with the ADV7180. The ADV7180 implements a patented Adaptive Digital Line Length Tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7180 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7180 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The video processor can process a variety of VBI data services, such as closed captioning (CCAP), wide-screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar(R) 1x/2x, and extended data service (XDS). Teletext data slicing for world standard teletext (WST), along with program delivery control (PDC) and video programming service (VPS), are provided. Data is transmitted via the 8-bit video output port as ancillary data packets (ANC). The ADV7180 is fully Macrovision certified; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs.
ANALOG FRONT END
The ADV7180 analog front end comprises a single high speed, 10-bit, analog-to-digital converter (ADC) that digitizes the analog video signal before applying it to the standard definition processor. The analog front end employs differential channels to the ADC to ensure high performance in mixed-signal applications. The front end also includes a 3-channel input mux that enables multiple composite video signals to be applied to the ADV7180. Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter. A resistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the ADC (see Figure 24). Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7180. Table 1 shows the three ADC clocking rates, which are determined by the video input format to be processed--that is, INSEL[3:0]. These clock rates ensure 4x oversampling per channel for CVBS mode and 2x oversampling per channel for Y/C and YPrPb modes. Table 1. ADC Clock Rates
Input Format CVBS Y/C (S-Video) 2 YPrPb
1 2
ADC Clock Rate 1 57.27 MHz 86 MHz 86 MHz
Oversampling Rate per Channel 4x 2x 2x
Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins. Refer to INSEL[3:0] in Table 103 for the mandatory write for Y/C (S-video) mode.
Rev. A | Page 4 of 112
ADV7180
COMPARISON WITH THE ADV7181B
In comparison with the ADV7181B, the ADV7180 LQFP-64 has the following additional features: * * * * * * Improved VCR and weak tuner locking capabilities Three on-chip antialiasing filters Four general-purpose outputs (GPOs) 1.8 V analog supply voltage 40-lead LFCSP option Automatic power-down of unused channels when using INSEL[3:0]
0.1F VREFN 0.1F VREFP
05700-002
Pin Compatibility with the ADV7181B
The ADV7180 LQFP-64 is pin compatible with the ADV7181B. A complete ADV7181B-to-ADV7180 change over document is available on request that specifies software changes required to make the transition. Contact Analog Devices local field engineers for more information. Please note that the ADV7180 has a different ADC reference decoupling circuit (shown in Figure 2) than the ADV7181B.
0.1F
Figure 2. ADV7180 ADC Reference Decoupling Circuit
Rev. A | Page 5 of 112
ADV7180 FUNCTIONAL BLOCK DIAGRAMS
XTAL1 XTAL CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC
FIFO
AIN1 ANALOG VIDEO INPUTS AIN2 AIN3 AIN4 AIN5 AIN6
MUX BLOCK
OUTPUT BLOCK
AA FILTER AA FILTER AA FILTER
10-BIT, 86MHz ADC
DIGITAL PROCESSING BLOCK 2D COMB
16-BIT PIXEL DATA P15 TO P0 HS VS FIELD GPO0 TO GPO3 SFL INTRQ
05700-003
SHA
A/D
VBI SLICER COLOR DEMOD
REFERENCE
I2C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
Figure 3. Functional Block Diagram (64-Lead LQFP)
XTAL1 XTAL
CLOCK PROCESSING BLOCK PLL ADLLT PROCESSING LLC
FIFO
MUX BLOCK
OUTPUT BLOCK
AIN1 ANALOG VIDEO INPUTS AIN2 AIN3
AA FILTER AA FILTER AA FILTER
10-BIT, 86MHz ADC
DIGITAL PROCESSING BLOCK 2D COMB
8-BIT PIXEL DATA P7 TO P0 HS VS/FIELD SFL INTRQ
05700-004
SHA
A/D
VBI SLICER COLOR DEMOD
REFERENCE
I2C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
Figure 4. Functional Block Diagram (40-Lead LFCSP)
Rev. A | Page 6 of 112
ADV7180 SPECIFICATIONS
Temperature range: TMIN to TMAX is -40C to +85C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS
At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Crystal Inputs Crystal Inputs Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1 Digital Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current Symbol N INL DNL VIH VIL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD ISOURCE = 0.4 mA ISINK = 3.2 mA Test Conditions Min Typ Max 10 BSL in CVBS mode CVBS mode 2 0.8 1.2 -10 0.4 +10 10 2 -0.6/+0.6 Unit Bits LSB LSB V V V V A pF V V A pF V V V V mA mA mA mA mA mA A A A A W ms
2.4 0.4 10 20 1.65 3.0 1.65 1.71 1.8 3.3 1.8 1.8 77 3 12 33 59 77 6 0.1 1 1 15 20 2 3.6 2.0 1.89
CVBS input Y/C input YPrPb input
Power-Down Current
IDVDD IDVDDIO IPVDD IAVDD tPWRUP
Total Power Dissipation in Power-Down Mode 2 Power-Up Time
1 2
Guaranteed by characterization. ADV7180 clocked.
Rev. A | Page 7 of 112
ADV7180
VIDEO SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 3.
Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock-In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed Chroma Lima Gain Delay Symbol DP DG LNL Test Conditions CVBS input, modulate 5-step [NTSC] CVBS input, modulate 5-step [NTSC] CVBS input, 5-step [NTSC] Luma ramp Luma flat field Min Typ 0.6 0.5 2.0 57.1 58 60 -5 40 1.3 60 20 5 2 100 2.9 5.6 -3.0 CVBS, 1 V input CVBS, 1 V input 1 1 200 200 +5 70 Max Unit Degrees % % dB dB dB % Hz kHz Lines % % Fields Lines ns ns ns % %
CVBS Y/C YPrPb
LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy
Rev. A | Page 8 of 112
ADV7180
TIMING SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 4.
Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Times SCLK and SDA Fall Times Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Data Output Transitional Time Symbol Test Conditions Min Typ 28.6363 50 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t12 Negative clock edge to start of valid data (tACCESS = t10 - t11) End of valid data to negative clock edge (tHOLD = t9 + t12) 45:55 55:45 3.6 2.4 Max Unit MHz ppm kHz s s s s ns ns ns s ms % duty cycle ns ns
ANALOG SPECIFICATIONS
Guaranteed by characterization. At AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified at operating temperature range, unless otherwise noted. Table 5.
Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large-Clamp Source Current Large-Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions Min Typ 0.1 10 0.4 0.4 10 10 Max Unit F M mA mA A A
Clamps switched off
THERMAL SPECIFICATIONS
Table 6.
Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol JA JC JA JC Test Conditions 4-layer PCB with solid ground plane, 40-lead LFCSP 4-layer PCB with solid ground plane, 40-lead LFCSP 4-layer PCB with solid ground plane, 64-lead LQFP 4-layer PCB with solid ground plane, 64-lead LQFP
Rev. A | Page 9 of 112
Min
Typ 30 3 47 11.1
Max
Unit C/W C/W C/W C/W
ADV7180
TIMING DIAGRAMS
t3
SDATA
t5
t3
t6
SCLK
t1 t4
05700-005 05700-006
t2
t7
t8
Figure 5. I C Timing
2
t9
OUTPUT LLC
t10
OUTPUTS P0-P15, VS, HS, FIELD, SFL
t12
t11
Figure 6. Pixel Port and Control Output Timing
Rev. A | Page 10 of 112
ADV7180 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage Digital Output Voltage Analog Inputs to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 4V -0.3 V to +2 V -0.3 V to +0.9 V -0.3 V to +2 V -0.3 V to +2 V -0.3 V to +0.3 V -0.3 V to +0.9 V DGND - 0.3 V to DVDDIO + 0.3 V DGND - 0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 125C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
ESD CAUTION
Rev. A | Page 11 of 112
ADV7180 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
40-LEAD LFCSP
DGND HS INTRQ VS/FIELD DVDD DGND SCLK SDATA ALSB RESET
DVDDIO 1 SFL 2 DGND 3 DVDDIO 4 P7 5 P6 6 P5 7 P4 8 P3 9 P2 10
40 39 38 37 36 35 34 33 32 31
PIN 1 INDICATOR
ADV7180
LFCSP TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
AIN3 AIN2 AGND AVDD VREFN VREFP AGND AIN1 TEST_0 AGND
LLC XTAL1 XTAL DVDD DGND P1 P0 PWRDWN ELPF PVDD
11 12 13 14 15 16 17 18 19 20
Figure 7. 40-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions for the ADV7180 LFCSP-40
Pin No. 3, 15, 35, 40 21, 24, 28 1, 4 14, 36 27 20 23, 29, 30 5 to 10, 16, 17 39 38 37 33 34 32 31 11 13 12 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1 to AIN3 P7 to P2, P1, P0 HS INTRQ VS/FIELD SDATA SCLK ALSB RESET LLC XTAL XTAL1 Type G G P P P P I O O O O I/O I I I O I O Function Ground for Digital Supply. Ground for Analog Supply. Digital I/O Supply Voltage (3.3 V). Digital Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels. Video Pixel Output Port. Horizontal Synchronization Output Signal. Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video (see Table 104). Vertical Synchronization Output Signal/Field Synchronization Output Signal. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. Selects the I2C Address for the ADV7180. For ALSB set to Logic 0, the address selected for a write is 0xTBC; for ALSB set to logic high, the address selected is 0xTBC. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry. Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz, but varies up or down according to video line length. Input Pin for the 28.6363 MHz Crystal. Can be overdriven by an external 1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 28.6363 MHz crystal, or not connected if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal must be a fundamental crystal. A logic low on this pin places the ADV7180 into power-down mode. The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 53. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Internal Voltage Reference Output. See Figure 53 for recommended output circuitry. Internal Voltage Reference Output. See Figure 53 for recommended output circuitry. This pin must be tied to DGND.
Rev. A | Page 12 of 112
18 19 2
PWRDWN ELPF SFL
I I O
26 25 22
VREFN VREFP TEST_0
O O I
05700-007
ADV7180
64-LEAD LQFP
RESET SDATA FIELD DGND DVDD GPO2 GPO3 SCLK ALSB AIN6
48 AIN5 PIN 1 47 AIN4 46 AIN3 45 NC 44 NC 43 AGND 42 NC 41 NC 40 AVDD 39 VREFN 38 VREFP 37 AGND 36 AIN2 35 AIN1 34 TEST_0 33 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P12
P13
P14
P15
64 63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
INTRQ HS DGND DVDDIO P11 P10 P9 P8 SFL
1 2 3 4 5 6 7 8 9
ADV7180
LQFP TOP VIEW (Not to Scale)
DGND 10 DVDDIO 11 GPO1 12 GPO0 13 P7 14 P6 15 P5 16
LLC
XTAL
XTAL1
PWRDWN
ELPF
P4
P3
P2
P1
P0
DGND
PVDD
NC
NC
NC
VS
AGND
DVDD
NC = NO CONNECT
Figure 8. 64-Lead LQFP Pin Configuration
Table 9. Pin Function Description for the ADV7180 LQFP-64
Pin No. 3, 10, 24, 57 32, 37, 43 4, 11 23, 58 40 31 38 39 35, 36, 46 to 49 27, 28, 33, 41, 42, 44, 45, 50 5 to 8, 14 to 19, 25, 26, 59 to 62 2 64 63 1 53 54 52 29 30 51 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD VREFP VREFN AIN1 to AIN6 NC P11 to P8, P7 to P2, P1, P0, P15 to P12 HS VS FIELD INTRQ SDATA SCLK ALSB PWRDWN ELPF RESET O Type G G P P P P O O I Function Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). PLL Supply Voltage (1.8 V). Internal Voltage Reference Output. See Figure 54 for recommended output circuitry. Internal Voltage Reference Output. See Figure 54 for recommended output circuitry. Analog Video Input Channels. No Connect Pins. These pins are not connected internally. Video Pixel Output Port. See Table 96 for output configuration for 8-bit and 16-bit modes.
O O O O I/O I I I I I
Horizontal Synchronization Output Signal. Vertical Synchronization Output Signal. Field Synchronization Output Signal. Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video (see Table 104). I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. This pin selects the I2C address for the ADV7180. For ALSB set to Logic 0, the address selected for a write is 0x40; for ALSB set to logic high, the address selected is 0x42. A logic low on this pin places the ADV7180 in power-down mode. The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 54. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7180 circuitry.
Rev. A | Page 13 of 113
05700-008
ADV7180
Pin No. 9 Mnemonic SFL Type O Function Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally 27 MHz, but varies up or down according to video line length. This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal must be a fundamental crystal. This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices. This pin must be tied to DGND.
20 21
LLC XTAL1
O O
22
XTAL
I
12, 13, 55, 56 34
GPO0 to GPO3 TEST_0
O I
Rev. A | Page 14 of 113
ADV7180 ANALOG FRONT END
MAN_MUX_EN
AIN2 AIN1 AIN4 AIN3 AIN6 AIN5
AIN2 AIN1 AIN4 AIN3 AIN6 AIN5 AIN4 AIN3 AIN6 AIN5
MUX_0[3:0]
MUX_1[3:0]
ADC AIN6 AIN5
MUX_2[3:0]
05700-009
Figure 9. Internal Pin Connections LQFP-64
MAN_MUX_EN
AIN1 AIN2 AIN3
AIN1 AIN2 AIN3
MUX_0[3:0]
AIN2 AIN3
MUX_1[3:0] ADC
AIN3
MUX_2[3:0]
05700-010
Figure 10. Internal Pin Connections LFCSP-40
Rev. A | Page 15 of 112
ADV7180
INPUT CONFIGURATION
There are two key steps for configuring the ADV7180 to correctly decode the input video. 1. Use INSEL[3:0] to configure routing and format decoding (CVBS, Y/C, or YPrPb). For the ADV7180 LQFP-64, see Table 10. For ADV7180 LFCSP-40, see Table 11. If the input requirements are not met using the INSEL[3:0] options, the analog input muxing section must be configured manually to correctly route the video from the analog input pins to the ADC. The standard definition processor block, which decodes the digital data, should be configured to process either CVBS, Y/C, or YPrPb format. This is performed by INSEL[3:0] selection.
CONNECT ANALOG VIDEO SIGNALS TO ADV7180.
Table 10. ADV7180 LQFP-64 INSEL[3:0]
INSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Video Format Composite Composite Composite Composite Composite Composite Y/C (S-video) Y/C (S-video) Y/C (S-video) YPrPb Analog Input CVBS AIN1 CVBS AIN2 CVBS AIN3 CVBS AIN4 CVBS AIN5 CVBS AIN6 Y AIN1 C AIN4 Y AIN2 C AIN5 Y AIN3 C AIN6 Y AIN1 Pb AIN4 Pr AIN5 Y AIN2 Pr AIN6 Pb AIN3 Not used
2.
SET INSEL[3:0] TO CONFIGURE VIDEO FORMAT. USE PREDEFINED FORMAT/ROUTING.
1010
YPrPb
NO YES LQFP-64 LFCSP-40 CONFIGURE ADC INPUTS USING MANUAL MUXING CONTROL BITS: MUX_0[3:0], MUX_1[3:0], MUX_2[3:0]. SEE TABLE 12.
1011 to 1111
Not used
REFER TO TABLE 10
REFER TO TABLE 11
05700-011
Table 11. ADV7180 LFCSP-40 INSEL[3:0]
INSEL[3:0] 0000 0001 to 0010 0011 0100 0101 0110 0111 to 1000 1001 Video Format Composite Not used Composite Composite Not used Y/C (S-video) Not used YPrPb Analog Input CVBS AIN1 Not used CVBS AIN2 CVBS AIN3 Not used Y AIN1 C AIN2 Not used Y AIN1 Pr AIN3 Pb AIN2 Not used
Figure 11. Signal Routing Options
INSEL[3:0], INPUT SELECTION, ADDRESS 0x00 [3:0]
The INSEL bits allow the user to select the input format. They also configure the standard definition processor core to process composite (CVBS), S-video (Y/C), or component (YPrPb) format. INSEL[3:0] has predefined analog input routing schemes that do not require manual mux programming (see Table 10 and Table 11). This allows the user to route the various video signal types to the decoder and select them using INSEL[3:0] only. The added benefit is that if, for example, CVBS input is selected, the remaining channels are powered down.
1010 to 1111
Not used
Rev. A | Page 16 of 112
ADV7180
ANALOG INPUT MUXING
The ADV7180 has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. Figure 9 and Figure 10 outline the overall structure of the input muxing provided in the ADV7180. A maximum of six CVBS inputs can be connected to and decoded by the ADV7180BSTZ (64-lead LQFP) and a maximum of three for ADV7180BCPZ (40-lead LFCSP). As shown in the Pin Configurations and Function Description section, these analog input pins lie in close proximity to one another. This calls for a careful design of the PCB layout; for example, ground shielding between all signals should be routed through tracks that are physically close together. It is strongly recommended to connect any unused analog input pins to AGND to act as a shield.
MAN_MUX_EN, Manual Input Muxing Enable, Address 0xC4 [7]
To configure the ADV7180 analog muxing section, the user must select the analog input AIN1 to AIN6 (ADV7180BSTZ) or AIN1 to AIN3 (ADV7180BCPZ) that is to be processed by the ADC. MAN_MUX_EN must be set to 1 to enable the following muxing blocks: * * * MUX_0[3:0], ADC Mux Configuration, Address 0xC3 [3:0] MUX_1[3:0], ADC Mux Configuration, Address 0xC3 [7:4] MUX_2[3:0], ADC Mux Configuration, Address 0xC4 [3:0]
The three mux sections are controlled by the signal buses SW_0/1/2[3:0]. Table 12 explains the control words used. The input signal that contains the timing information (HS and VS) must be processed by MUX_0. For example, in a Y/C input configuration, MUX0 should be connected to the Y channel and MUX1 to the C channel. When one or more muxes are not used to process video, such as CVBS input, the idle mux and associated channel clamps and buffers should be powered down (see the description of Register 0x3A in Table 103).
Table 12. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)
MUX_0[3:0] 000 001 010 011 100 101 110 111 ADC Connected to LQFP-64 LFCSP-40 No connect No connect AIN1 AIN1 AIN2 No connect AIN3 No connect AIN4 AIN2 AIN5 AIN3 AIN6 No connect No connect No connect MUX_1[3:0] 000 001 010 011 100 101 110 111 ADC Connected to LQFP-64 LFCSP-40 No connect No connect No connect No connect No connect No connect AIN3 No connect AIN4 AIN2 AIN5 AIN3 AIN6 No connect No connect No connect MUX_2[3:0] 000 001 010 011 100 101 110 111 ADC Connected to LQFP-64 LFCSP-40 No connect No connect No connect No connect AIN2 No connect No connect No connect No connect No connect AIN5 AIN3 AIN6 No connect No connect No connect
Note the following: * * * CVBS can only be processed by MUX_0. Y/C can only be processed by MUX_0 and MUX_1, respectively. YPrPb can only be processed by MUX_0, MUX_1, and MUX_2, respectively.
Rev. A | Page 17 of 112
ADV7180
ANTIALIASING FILTERS
The ADV7180 has optional on-chip antialiasing filters on each of the three channels that are multiplexed to the ADC (see Figure 12). The filters are designed for standard definition video up to 10 MHz bandwidth. Figure 13 and Figure 14 show the filter magnitude and phase characteristics. The antialiasing filters are enabled by default and the selection of INSEL[3:0] determines which filters are powered up at any given time. For example, if CVBS mode is selected, the filter circuits for the remaining input channels are powered down to conserve power. However, the antialiasing filters can be disabled or bypassed using the AA_FILT_MAN_OVR control.
AIN1 10-BIT, 86MHz ADC AA FILTER 1
AA_FILT_EN, Address 0xF3 [1]
When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed. When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.
AA_FILT_EN, Address 0xF3 [2]
When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed. When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.
0 -4 -8 -12 -16 -20
AIN3 AIN41 AIN51 AIN61
MUX BLOCK
AIN2
AA FILTER 2 AA FILTER 3
SHA
A/D
-24 -28
05700-013
-32
05700-012
-36 1k
10k
100k
1M
10M
100M
1ONLY
AVAILABLE IN 64-LEAD PACKAGE
FREQUENCY (Hz)
Figure 12. Antialias Filter Configuration
Figure 13. Antialiasing Filter Magnitude Response
AA_FILT_MAN_OVR, Antialiasing Filter Override, Address 0xF3 [3]
This feature allows the user to override the antialiasing filters on/off settings, which are automatically selected by INSEL[3:0].
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -140 -150 1k 10k 100k 1M 10M
05700-014
AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3 [2:0]
These bits allow the user to enable or disable the antialiasing filters on each of the three input channels multiplexed to the ADC. When disabled, the analog signal bypasses the AA filter and is routed directly to the ADC.
AA_FILT_EN, Address 0xF3 [0]
When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed. When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.
-130
100M
FREQUENCY (Hz)
Figure 14. Antialiasing Filter Phase Response
Rev. A | Page 18 of 112
ADV7180 GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip. After setting the RESET bit (or initiating a reset via the RESET pin), the part returns to the default for its primary mode of operation. All I2C bits are loaded with their default values, making this bit self-clearing. Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed. The I2C master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented. See the MPU Port Description section. When RESET is 0 (default), operation is normal. When RESET is 1, the reset sequence starts.
POWER-SAVING MODES
Power-Down PDBP, Address 0x0F [2]
The digital supply of the ADV7180 can be shut down by using the (PWRDWN) pin or via I2C (PWRDWN, see below). PDBP controls whether the I2C control or the pin has the higher priority. The default is to give the pin (PWRDWN) priority. This allows the user to have the ADV7180 powered down by default at power-up without the need for an I2C write. When PDBD is 0 (default), the digital supply power is controlled by the PWRDWN pin (the PWRDWN bit is disregarded). When PDBD is 1, the PWRDWN bit, 0x0F[5], has priority (the pin is disregarded).
GLOBAL PIN CONTROL
Three-State Output Drivers TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the ADV7180. Upon setting the TOD bit, the P15 to P0 (P7 to P0 for the ADV7180 LFCSP-40), HS, VS, FIELD (VS/FIELD pin for the ADV7180 LFCSP-40), and SFL pins are three-stated. The timing pins (HS, VS, FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the Three-State LLC Driver and the Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_XX bits. When TOD is 0 (default), the output drivers are enabled. When TOD is 1, the output drivers are three-stated.
PWRDWN, Address 0x0F [5]
When PDBP is set to 1, setting the PWRDWN bit switches the ADV7180 to a chip-wide power-down mode. The power-down stops the clock from entering the digital section of the chip, thereby freezing its operation. No I2C bits are lost during power-down. The PWRDWN bit also affects the analog blocks and switches them into low current modes. The I2C interface is unaffected and remains operational in power-down mode. The ADV7180 leaves the power-down state if the PWRDWN bit is set to 0 (via I2C) or if the ADV7180 is reset using the RESET pin. PDBP must be set to 1 for the PWRDWN bit to power down the ADV7180. When PWRDWN is 0 (default), the chip is operational. When PWRDWN is 1, the ADV7180 is in a chip-wide power-down mode.
RESET CONTROL
RESET, Chip Reset, Address 0x0F [7]
Setting this bit, which is equivalent to controlling the RESET pin on the ADV7180, issues a full chip reset. All I2C registers are reset to their default/power-up values. Note that some register bits do not have a reset value specified. They keep their last written value. Those bits are marked as having a reset value of x in the register tables (Table 103 and Table 104). After the reset sequence, the part immediately starts to acquire the incoming video signal.
Three-State LLC Driver TRI_LLC, Address 0x1D [7]
This bit allows the output drivers for the LLC pin of the ADV7180 to be three-stated. For more information on threestate control, refer to the Three-State Output Drivers and the Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_XX bits. When TRI_LLC is 0 (default), the LLC pin drivers work according to the DR_STR_C[1:0] setting (pin enabled). When TRI_LLC is 1, the LLC pin drivers are three-stated.
Rev. A | Page 19 of 112
ADV7180
Timing Signals Output Enable TIM_OE, Address 0x04 [3]
The TIM_OE bit should be regarded as an addition to the TOD bit. Setting it high forces the output drivers for HS, VS, and FIELD into the active state (that is, driving state) even if the TOD bit is set. If TIM_OE is set to low, the HS, VS, and FIELD pins are three-stated depending on the TOD bit. This functionality is beneficial if the decoder is to be used as a timing generator only. This may be the case if only the timing signals are to be extracted from an incoming signal, or if the part is in free-run mode, where a separate chip can output a company logo, for example. For more information on three-state control, refer to the Three-State Output Drivers section and the Three-State LLC Driver section. Individual drive strength controls are provided via the DR_STR_XX bits. When TIM_OE is 0 (default), HS, VS, and FIELD are threestated according to the TOD bit. When TIM_OE is 1, HS, VS, and FIELD are forced active all the time. Table 14. DR_STR_C Function
DR_STR_C[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x)
Drive Strength Selection (Sync) DR_STR_S[1:0], Address 0xF4 [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals with which HS, VS, and FIELD are driven. For more information, refer to the Drive Strength Selection (Data) section. Table 15. DR_STR_S Function
DR_STR_S[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x)
Enable Subcarrier Frequency Lock Pin EN_SFL_PIN, Address 0x04 [1]
The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as Genlock) from the ADV7180 core to an encoder in a decoder/encoder back-to-back arrangement. When EN_SFL_PIN is 0 (default), the subcarrier frequency lock output is disabled. When EN_SFL_PIN is 1, the subcarrier frequency lock information is presented on the SFL pin.
Drive Strength Selection (Data) DR_STR[1:0], Address 0xF4 [5:4]
For EMC and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[15:0] output drivers. For more information on three-state control, refer to the Drive Strength Selection (Clock) and the Drive Strength Selection (Sync) sections. Table 13. DR_STR Function
DR_STR[1:0] 00 01 (default) 10 11 Description Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x)
Polarity LLC Pin PCLK, Address 0x37 [0]
The polarity of the clock that leaves the ADV7180 via the LLC pin can be inverted using the PCLK bit. Changing the polarity of the LLC clock output may be necessary to meet the setup-and-hold time expectations of follow-on chips. When PCLK is 0, the LLC output polarity is inverted. When PCLK is 1 (default), the LLC output polarity is normal (see the Timing Specifications section).
Drive Strength Selection (Clock) DR_STR_C[1:0], Address 0xF4 [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Drive Strength Selection (Sync) and the Drive Strength Selection (Data) sections.
Rev. A | Page 20 of 112
ADV7180 GLOBAL STATUS REGISTER
Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7180. The other three registers contain status bits from the ADV7180. Table 17. Status_1 Function
STATUS_1 [7:0] 0 1 2 3 4 5 6 7 Bit Name IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT[0] AD_RESULT[1] AD_RESULT[2] COL_KILL Description In lock (now) Lost lock (since last read of this register) FSC locked (now) AGC follows peak white algorithm Result of autodetection Result of autodetection Result of autodetection Color kill active
IDENTIFICATION
IDENT[7:0], Address 0x11 [7:0]
The register identification of the revision of the ADV7180. An identification value of 0x18 indicates the ADV7180.
STATUS 1
STATUS_1[7:0], Address 0x10 [7:0]
This read-only register provides information about the internal status of the ADV7180. See the CIL[2:0], Count Into Lock, Address 0x51 [2:0] section and the COL[2:0], Count Out of Lock, Address 0x51 [5:3] section for details on timing. Depending on the setting of the FSCLE bit, the Status Register 0 and Status Register 1 are based solely on horizontal timing information or on the horizontal timing and lock status of the color subcarrier. See the FSCLE, FSC Lock Enable, Address 0x51 [7] section.
STATUS 2
STATUS_2[7:0], Address 0x12 [7:0]
Table 18. STATUS_2 Function
STATUS_2 [7:0] 0 1 Bit Name MVCS DET MVCS T3 Description Detected Macrovision color striping Macrovision color striping protection; conforms to Type 3 if high, Type 2 if low Detected Macrovision pseudo sync pulses Detected Macrovision AGC pulses Line length is nonstandard FSC frequency is nonstandard
AUTODETECTION RESULT
AD_RESULT[2:0], Address 0x10 [6:4]
The AD_RESULT[2:0] bits report back on the findings from the ADV7180 autodetection block. Consult the General Setup section for more information on enabling the autodetection block and the Autodetection of SD Modes section for more information on how to configure it. Table 16. AD_RESULT Function
AD_RESULT[2:0] 000 001 010 011 100 101 110 111 Description NTSM M/J NTSC 4.43 PAL M PAL 60 PAL B/G/H/I/D SECAM PAL Combination N SECAM 525
2 3 4 5 6 7
MV PS DET MV AGC DET LL NSTD FSC NSTD Reserved Reserved
STATUS 3
STATUS_3[7:0], Address 0x13 [7:0]
Table 19. STATUS_3 Function
STATUS_3 [7:0] 0 1 2 3 4 Bit Name INST_HLOCK GEMD SD_OP_50Hz Description Horizontal lock indicator (instantaneous) Gemstar detect Flags whether 50 Hz or 60 Hz is present at output Reserved for future use ADV7180 outputs a blue screen (see the DEF_VAL_EN, Default Value Enable, Address 0x0C [0] section) Field length is correct for currently selected video standard Interlaced video detected (field sequence found) Reliable sequence of swinging bursts detected
FREE_RUN_ACT
5 6 7
STD FLD LEN INTERLACED PAL_SW_LOCK
Rev. A | Page 21 of 112
ADV7180 VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
MACROVISION DETECTION VBI DATA RECOVERY STANDARD AUTODETECTION SLLC CONTROL
DIGITIZED CVBS DIGITIZED Y (YC)
LUMA DIGITAL FINE CLAMP
LUMA FILTER
LUMA GAIN CONTROL
LUMA RESAMPLE
LUMA 2D COMB
SYNC EXTRACT
LINE LENGTH PREDICTOR
RESAMPLE CONTROL
AV CODE INSERTION
VIDEO DATA OUTPUT
DIGITIZED CVBS DIGITIZED C (YC)
CHROMA DIGITAL FINE CLAMP
CHROMA DEMOD
CHROMA FILTER
CHROMA GAIN CONTROL
CHROMA RESAMPLE
CHROMA 2D COMB
MEASUREMENT BLOCK ( I2C) VIDEO DATA PROCESSING BLOCK
05700-015
FSC RECOVERY
Figure 15. Block Diagram of the Video Processor
Figure 15 shows a block diagram of the ADV7180 video processor. The ADV7180 can handle standard definition video in CVBS, Y/C, and YPrPb formats. It can be divided into a luminance and chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.
SD CHROMA PATH
The input signal is processed by the following blocks: * Chroma Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Chroma Demodulation. This block employs a color subcarrier (FSC) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM. Chroma Filter. This block contains a chroma decimation filter (CAA) with a fixed response and some shaping filters (CSH) that have selectable responses. Chroma Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic line-length errors of the incoming video signal. Chroma 2D Comb. The 2D, 5-line, superadaptive comb filter provides high quality Y/C separation in case the input signal is CVBS.
SD LUMA PATH
The input signal is processed by the following blocks: * Luma Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Luma Filter. This block contains a luma decimation filter (YAA) with a fixed response and some shaping filters (YSH) that have selectable responses. Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. Luma Resample. To correct for line-length errors as well as dynamic linelength changes, the data is digitally resampled. Luma 2D Comb. The two-dimensional comb filter provides Y/C separation. AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes can be inserted (as per ITU-R BT.656).
*
*
*
*
*
*
*
* *
*
Rev. A | Page 22 of 112
ADV7180
* AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes can be inserted (as per ITU-R BT.656).
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] register allows the user to force the digital core into a specific video standard. Under normal circumstances, this is not necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The following section provides more information on the autodetection system.
SYNC PROCESSING
The ADV7180 extracts syncs embedded in the analog input video signal. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure that the ADV7180 outputs 720 active pixels per line. The sync processing on the ADV7180 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video: * VSYNC Processor. This block provides extra filtering of the detected VSYNCs to improve vertical lock. HSYNC Processor. The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise, providing much improved performance for video signals with a stable time base but poor SNR.
Autodetection of SD Modes
To guide the autodetect system of the ADV7180, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection block can be read back via the status registers. See the Global Status Register section for more information.
VID_SEL[3:0], Address 0x00 [7:4]
Table 20. VID_SEL Function
VID_SEL[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Autodetect (PAL B/G/H/I/D) <-> NTSC J (no pedestal), SECAM Autodetect (PAL B/G/H/I/D) <-> NTSC M (pedestal), SECAM Autodetect (PAL N) (pedestal) <-> NTSC J (no pedestal), SECAM Autodetect (PAL N) (pedestal) <-> NTSC M (pedestal), SECAM NTSC J (1) NTSC M (1) PAL 60 NTSC 4.43 (1) PAL B/G/H/I/D PAL N = PAL B/G/H/I/D (with pedestal) PAL M (without pedestal) PAL M PAL Combination N PAL Combination N (with pedestal) SECAM SECAM (with pedestal)
*
VBI DATA RECOVERY
The ADV7180 can retrieve the following information from the input video: * * * * * * * * Wide-screen signaling (WSS) Copy generation management system (CGMS) Closed captioning (CCAP) Macrovision protection presence EDTV data Gemstar-compatible data slicing Teletext VITC/VPS
AD_SEC525_EN, Enable Autodetection of SECAM 525 Line Video, Address 0x07 [7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection of a 525-line system with a SECAM-style, FMmodulated color component. Setting AD_SEC525_EN to 1 enables the detection of a SECAM-style, FM-modulated color component.
The ADV7180 is also capable of automatically detecting the incoming video standard with respect to * * * Color subcarrier frequency Field rate Line rate
The ADV7180 can configure itself to support PAL B/G/H/I/D, PAL M/N, PAL Combination N, NTSC M, NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.
Rev. A | Page 23 of 112
ADV7180
AD_SECAM_EN, Enable Autodetection of SECAM, Address 0x07 [6]
Setting AD_SECAM_EN to 0 (default) disables the autodetection of SECAM. Setting AD_SECAM_EN to 1 enables the detection of SECAM.
AD_PAL_EN, Enable Autodetection of PAL, Address 0x07 [0]
Setting AD_PAL_EN to 0 (default) disables the detection of standard PAL. Setting AD_PAL_EN to 1 enables the detection of standard PAL.
AD_N443_EN, Enable Autodetection of NTSC 4.43, Address 0x07 [5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection of NTSC style systems with a 4.43 MHz color subcarrier.
SFL_INV, Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL (Genlock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems. First, the PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC. Second, there was a design change in Analog Devices encoders from ADV717x to ADV719x. The older versions used the SFL (Genlock Telegram) bit directly, whereas the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the one-line delay of an SFL (Genlock Telegram) transmission. As a result, ADV717x encoders need the PAL switch bit in the SFL (GenLock Telegram) to be 1 for NTSC to work. Also, ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180 phase shift occurs. In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used.
AD_P60_EN, Enable Autodetection of PAL 60, Address 0x07 [4]
Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate. Setting AD_P60_EN to 1 (default) enables the detection of PAL systems with a 60 Hz field rate.
AD_PALN_EN, Enable Autodetection of PAL N, Address 0x07 [3]
Setting AD_PALN_EN to 0 (default) disables the detection of the PAL N standard. Setting AD_PALN_EN to 1 enables the detection of the PAL N standard.
AD_PALM_EN, Enable Autodetection of PAL M, Address 0x07 [2]
Setting AD_PALM_EN to 0 (default) disables the autodetection of PAL M. Setting AD_PALM_EN to 1 enables the detection of PAL M.
SFL_INV, Subcarrier Frequency Lock Inversion, Address 0x41 [6]
Setting SFL_INV to 0 (default) makes the part SFL-compatible with ADV7190/ADV7191/ADV7194 encoders. Setting SFL_INV to 1 makes the part SFL-compatible with ADV717x and ADV7173x encoders.
AD_NTSC_EN, Enable Autodetection of NTSC, Address 0x07 [1]
Setting AD_NTSC_EN to 0 (default) disables the detection of standard NTSC. Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.
Lock Related Controls
Lock information is presented to the user through Bits[1:0] of the Status Register 1. See the STATUS_1[7:0], Address 0x10 [7:0] section. Figure 16 outlines the signal flow and the controls available to influence the way the lock status information is generated.
FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0]
SELECT THE RAW LOCK SIGNAL SRLS TIME_WIN FREE_RUN FSC LOCK TAKE FSC LOCK INTO ACCOUNT FSCLE 1 0
0 1
COUNTER INTO LOCK COUNTER OUT OF LOCK MEMORY
STATUS_1 [0] STATUS_1 [1]
05700-016
Figure 16. Lock Related Signal Path
Rev. A | Page 24 of 112
ADV7180
SRLS, Select Raw Lock Signal, Address 0x51 [6]
Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status Register 1). Refer to Figure 16. * The TIME_WIN signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly. The FREE_RUN signal evaluates the properties of the incoming video over several fields, taking vertical synchronization information into account.
COL[2:0], Count Out of Lock, Address 0x51 [5:3]
COL[2:0] determines the number of consecutive lines for which the out-of-lock condition must be true before the system switches into the unlocked state and reports this via Status 0 [1:0]. It counts the value in lines of video. Table 22. COL Function
COL[2:0] 000 001 010 011 100 (default) 101 110 111 Number of Video Lines 1 2 5 10 100 500 1000 100,000
*
Setting SRLS to 0 (default) selects the FREE_RUN signal. Setting SRLS to 1 selects the TIME_WIN signal.
FSCLE, FSC Lock Enable, Address 0x51 [7]
The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits[1:0] in Status Register 1. This bit must be set to 0 when operating the ADV7180 in YPrPb component mode in order to generate a reliable HLOCK status bit. When FSCLE is set to 0 (default), only the overall lock status is dependent on horizontal sync lock. When FSCLE is set to 1, the overall lock status is dependent on horizontal sync lock and FSC lock.
COLOR CONTROLS
These registers allow the user to control picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent from picture clamping, although both controls affect the dc level of the signal.
CON[7:0], Contrast Adjust, Address 0x08 [7:0]
This register allows the user to control contrast adjustment of the picture. Table 23. CON Function
CON[7:0] 0x80 (default) 0x00 0xFF Description Gain on luma channel = 1 Gain on luma channel = 0 Gain on luma channel = 2
CIL[2:0], Count Into Lock, Address 0x51 [2:0]
CIL[2:0] determines the number of consecutive lines for which the into lock condition must be true before the system switches into the locked state and reports this via Status 0 [1:0]. The bit counts the value in lines of video. Table 21. CIL Function
CIL[2:0] 000 001 010 011 100 (default) 101 110 111 Number of Video Lines 1 2 5 10 100 500 1000 100,000
SD_SAT_Cb[7:0], SD Saturation Cb Channel, Address 0xE3 [7:0]
This register allows the user to control the gain of the Cb channel only, which in turn adjusts the saturation of the picture. Table 24. SD_SAT_Cb Function
SD_SAT_Cb[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cb channel = 0 dB Gain on Cb channel = -42 dB Gain on Cb channel = +6 dB
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ADV7180
SD_SAT_Cr[7:0], SD Saturation Cr Channel, Address 0xE4 [7:0]
This register allows the user to control the gain of the Cr channel only, which in turn adjusts the saturation of the picture. Table 25. SD_SAT_Cr Function
SD_SAT_Cr[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cr channel = 0 dB Gain on Cr channel = -42 dB Gain on Cr channel = +6 dB
Table 29. HUE Function
HUE[7:0] 0x00 (default) 0x7F 0x80 Description (Adjust Hue of the Picture) Phase of the chroma signal = 0 Phase of the chroma signal = -90 Phase of the chroma signal = +90
DEF_Y[5:0], Default Value Y, Address 0x0C [7:2]
When the ADV7180 loses lock on the incoming video signal or when there is no input signal, the DEF_Y[5:0] register allows the user to specify a default luma value to be output. This value is used under the following conditions: * If DEF_VAL_AUTO_EN bit is set to high and the ADV7180 has lost lock to the input video signal, this is the intended mode of operation (automatic mode). The DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. This is a forced mode that may be useful during configuration.
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1 [7:0]
This register allows the user to select an offset for the Cb channel only and to adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register. Table 26. SD_OFF_Cb Function
SD_OFF_Cb[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cb channel -312 mV offset applied to the Cb channel +312 mV offset applied to the Cb channel
*
The DEF_Y[5:0] values define the six MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}. For DEF_Y[5:0], 0x0D (blue) is the default value for Y. Register 0x0C has a default value of 0x36.
SD_OFF_Cr [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]
This register allows the user to select an offset for the Cr channel only and to adjust the hue of the picture. There is a functional overlap with the HUE[7:0] register. Table 27. SD_OFF_Cr Function
SD_OFF_Cr[7:0] 0x80 (default) 0x00 0xFF Description 0 offset applied to the Cr channel -312 mV offset applied to the Cr channel +312 mV offset applied to the Cr channel
DEF_C[7:0], Default Value C, Address 0x0D [7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the four MSBs of Cr and Cb values to be output if * * The DEF_VAL_AUTO_EN bit is set to high and the ADV7180 cannot lock to the input video (automatic mode). DEF_VAL_EN bit is set to high (forced output).
BRI[7:0], Brightness Adjust, Address 0x0A [7:0]
This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture. Table 28. BRI Function
BRI[7:0] 0x00 (default) 0x7F 0x80 Description Offset of the luma channel = 0IRE Offset of the luma channel = +100IRE Offset of the luma channel = -100IRE
The data that is finally output from the ADV7180 for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}. For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
DEF_VAL_EN, Default Value Enable, Address 0x0C [0]
This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions in the DEF_Y[5:0], Default Value Y, Address 0x0C [7:2] and DEF_C[7:0], Default Value C, Address 0x0D [7:0] sections for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS. Setting DEF_VAL_EN to 0 (default) outputs a colored screen determined by user-programmable Y, Cr, and Cb values when the decoder free-runs. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit. Setting DEF_VAL_EN to 1 forces a colored screen output determined by user-programmable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked.
HUE[7:0], Hue Adjust, Address 0x0B [7:0]
This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture. HUE[7:0] has a range of 90, with 0x00 equivalent to an adjustment of 0. The resolution of HUE[7:0] is 1 bit = 0.7. The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM-modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb).
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ADV7180
DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1]
This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7180 cannot lock to the video signal. Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If the decoder is unlocked, it outputs noise. Setting DEF_VAL_EN to 1 (default) enables free-run mode and a colored screen set by user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock. After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Because the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts, and must therefore be prohibited. The clamping scheme has to complete two tasks. It must acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. To acquire an unknown video signal quickly, the large current clamps should be activated. It is assumed that the amplitude of the video signal at this point is of a nominal value. Control of the coarse and fine current clamp parameters is performed automatically by the decoder. Standard definition video signals may have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7180 employs a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (see Figure 17). The following sections describe the I2C signals that can be used to influence the behavior of the clamping block.
CLAMP OPERATION
The input video is ac-coupled into the ADV7180. Therefore, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7180 and shows the different ways in which a user can configure its behavior. The ADV7180 uses a combination of current sources and a digital processing block for clamping, as shown in Figure 17. The analog processing channel shown is replicated three times inside the IC. While only one single channel is needed for a CVBS signal, two independent channels are needed for Y/C (S-VHS) type signals, and three independent channels are needed to allow component signals (YPrPb) to be processed. The clamping can be divided into two sections: * * Clamping before the ADC (analog domain): current sources. Clamping after the ADC (digital domain): digital processing block.
CCLEN, Current Clamp Enable, Address 0x14 [4]
The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether. This may be useful if the incoming analog video signal is clamped externally. When CCLEN is 0, the current sources are switched off. When CCLEN is 1 (default), the current sources are enabled.
The ADC can digitize an input signal only if it resides within the ADC 1.0 V input voltage range. An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range. The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits within the ADC range.
FINE CURRENT SOURCES
COARSE CURRENT SOURCES
ANALOG VIDEO INPUT
ADC
CLAMP CONTROL
Figure 17. Clamping Overview
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05700-017
DATA PREPROCESSOR (DPP)
VIDEO PROCESSOR WITH DIGITAL FINE CLAMP
ADV7180
DCT[1:0], Digital Clamp Timing, Address 0x15 [6:5]
The clamp timing register determines the time constant of the digital fine clamp circuitry. It is important to note that the digital fine clamp reacts very quickly because it is supposed to immediately correct any residual dc level error for the active line. The time constant from the digital fine clamp must be much quicker than the one from the analog blocks. By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. Table 30. DCT Function
DCT[1:0] 00 (default) 01 10 11 Description Slow (TC = 1 sec) Medium (TC = 0.5 sec) Fast (TC = 0.1 sec) Determined by ADV7180, depending on the input video parameters
*
Luma Shaping Filters (YSH). The shaping filter block is a programmable low-pass filter with a wide variety of responses. It can be used to selectively reduce the luma video signal bandwidth (needed prior to scaling, for example). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow-on video compression stage may work more efficiently if the video is low-pass filtered. The ADV7180 has two responses for the shaping filter: one that is used for good quality composite, component, and S-VHS type sources, and a second for nonstandard CVBS signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, using the comb filters for Y/C separation is recommended.
*
DCFE, Digital Clamp Freeze Enable, Address 0x15 [4]
This register bit allows the user to freeze the digital clamp loop at any time. It is intended for users who would like to do their own clamping. Users should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit. When DCFE to 0 (default), the digital clamp is operational. When DCFE is 1, the digital clamp loop is frozen.
Digital Resampling Filter. This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system with no requirement for user intervention.
Figure 19 through Figure 22 show the overall response of all filters together. Unless otherwise noted, the filters are set into a typical wideband mode.
Y Shaping Filter
For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. Y/C separation must aim for best possible crosstalk reduction while still retaining as much bandwidth (especially on the luma component) as possible. High quality Y/C separation can be achieved by using the internal comb filters of the ADV7180. Comb filtering, however, relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (FSC). For good quality CVBS signals, this relationship is known; the comb filter algorithms can be used to separate luma and chroma with high accuracy. In the case of nonstandard video signals, the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in the best fashion without the assistance of the shaping filter block.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets of filters. Note that the data format at this point is CVBS for CVBS input or luma only for Y/C and YPrPb input formats. * Luma Antialias Filter (YAA). The ADV7180 receives video at a rate of 27 MHz. (In the case of 4x oversampled video, the ADC samples at 57.27 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7180 is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a high quality linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter (YAA) has a fixed response.
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ADV7180
An automatic mode is provided that allows the ADV7180 to evaluate the quality of the incoming video signal and select the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override the automatic decisions in part or in full. The luma shaping filter has three control registers: * YSFM[4:0] allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (depending on video quality and video standard). WYSFMOVR allows the user to manually override the WYSFM decision. WYSFM[4:0] allows the user to select a different shaping filter mode for good quality composite (CVBS), component (YPrPb), and S-VHS (Y/C) input signals.
YSFM[4:0], Y Shaping Filter Mode, Address 0x17 [4:0]
The Y shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters. When switched in automatic mode, the filter selection is based on other register selections, such as detected video standard, as well as properties extracted from the incoming video itself, such as quality and time base stability. The automatic selection always selects the widest possible bandwidth for the video input encountered. * If the YSFM settings specify a filter (that is, YSFM is set to values other than 00000 or 00001), the chosen filter is applied to all video, regardless of its quality. In automatic selection mode, the notch filters are only used for bad quality video signals. For all other video signals, wideband filters are used.
* *
*
In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (because they can be successfully combed) as well as for luma components of YPrPb and Y/C sources (because they need not be combed). For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts. The decisions of the control logic are shown in Figure 18.
WYSFMOVR, Wideband Y Shaping Filter Override, Address 0x18 [7]
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 18. When WYSFMOVR is 0, the shaping filter for good quality video signals is selected automatically. Setting WYSFMOVR to 1 (default) enables manual override via WYSFM[4:0].
SET YSFM
YES
YSFM IN AUTO MODE? 00000 OR 00001
NO
VIDEO QUALITY BAD GOOD USE YSFM SELECTED FILTER REGARDLESS OF VIDEO QUALITY
AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB 1
WYSFMOVR 0
SELECT AUTOMATIC WIDEBAND FILTER
Figure 18. YSFM and WYSFM Control Flowchart
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05700-018
SELECT WIDEBAND FILTER AS PER WYSFM[4:0]
ADV7180
Table 31. YSFM Function
YSFM[4:0] 0'0000 0'0001 (default) 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011 1'0100 1'0101 1'0110 1'0111 1'1000 1'1001 1'1010 1'1011 1'1100 1'1101 1'1110 1'1111 Description Automatic selection including a wide-notch response (PAL/NTSC/SECAM) Automatic selection including a narrow-notch response (PAL/NTSC/SECAM) SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) PAL NN1 PAL NN2 PAL NN3 PAL WN1 PAL WN2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Reserved
Table 32. WYSFM Function
WYSFM[4:0] 0'0000 0'0001 0'0010 0'0011 0'0100 0'0101 0'0110 0'0111 0'1000 0'1001 0'1010 0'1011 0'1100 0'1101 0'1110 0'1111 1'0000 1'0001 1'0010 1'0011 (default) 1'0100 to 1'1111 Description Do not use Do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Do not use
The filter plots in Figure 19 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings. Figure 21 shows the PAL notch filter responses. The NTSC-compatible notches are shown in Figure 22.
COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE 0 -10 -20 -30 -40 -50 -60 -70
WYSFM[4:0], Wideband Y Shaping Filter Mode, Address 0x18 [4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with stable time base, luma component of YPrPb, and luma component of Y/C. The WYSFM bits are only active if the WYSFMOVR bit is set to 1. See the general discussion of the shaping filter settings in the Y Shaping Filter section.
AMPLITUDE (dB)
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 19. Y S-VHS Combined Responses
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05700-019
ADV7180
CHROMA FILTER
Data from the digital fine clamp block is processed by three sets of filters. Note that the data format at this point is CVBS for CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats. * Chroma Antialias Filter (CAA). The ADV7180 oversamples the CVBS by a factor of 4 and the chroma/YPrPb by a factor of 2. A decimating filter (CAA) is used to preserve the active video band and to remove any out-of-band components. The CAA filter has a fixed response. * * Chroma Shaping Filters (CSH). The shaping filter block (CSH) can be programmed to perform a variety of low-pass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression. Digital Resampling Filter. This block allows dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low-pass filters. The actual response is chosen by the system without user intervention.
Figure 23 shows the overall response of all filters together.
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE 0
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE 0 -10 -20 -30 -40 -50
-20
AMPLITUDE (dB)
-40
-60
-80
-100
05700-020
AMPLITUDE (dB)
-120
0
2
4
6
8
10
12
-70
0
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS, Y RESAMPLE 0 -10 -20 -30 -40 -50
Figure 22. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0
-10
ATTENUATION (dB)
AMPLITUDE (dB)
-20
-30
-40
05700-021
-70
-60
0
2
4
6
8
10
12
0
1
2
3
4
5
6
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
Figure 23. Chroma Shaping Filter Responses
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05700-023
-60
-50
05700-022
-60
ADV7180
CSFM[2:0], C Shaping Filter Mode, Address 0x17 [7:5]
The C shaping filter mode bits allow the user to select from a range of low-pass filters for the chrominance signal. When switched in automatic mode, the widest filter is selected based on the video standard/format and user choice (see Settings 000 and 001 in Table 33). Table 33. CSFM Function
CSFM[2:0] 000 (default) 001 010 011 100 101 110 111 Description Autoselect 1.5 MHz bandwidth Autoselect 2.17 MHz bandwidth SH1 SH2 SH3 SH4 SH5 Wideband mode
of the ADC, 0 V to 1 V. This circuit should be placed before all analog inputs to the ADV7180.
ANALOG VIDEO INPUT 36 100nF AIN_OF_ADV7180 39
05700-024
Figure 24. Input Voltage Divider Network
The minimum supported amplitude of the input video is determined by the ability of the ADV7180 to retrieve horizontal and vertical timing and to lock to the color burst, if present. There are separate gain control units for luma and chroma data. Both can operate independently of each other. The chroma unit, however, can also take its gain value from the luma path. The possible AGC modes are shown in Table 34. Table 34. AGC Modes
Input Video Type Any CVBS Luma Gain Manual gain luma Dependent on horizontal sync depth Peak white Chroma Gain Manual gain chroma Dependent on colorburst amplitude taken from luma path Dependent on colorburst amplitude taken from luma path Dependent on colorburst amplitude taken from luma path Dependent on colorburst amplitude Taken from luma path
Figure 23 shows the responses of SH1 (narrowest) to SH5 (widest) in addition to the wideband mode (shown in red).
GAIN OPERATION
The gain control within the ADV7180 is done on a purely digital basis. The input ADC supports a 10-bit range mapped into a 1.0 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. Advantages of this architecture over the commonly used programmable gain amplifier (PGA) before the ADC include the fact that the gain is now completely independent of supply, temperature, and process variations. As shown in Figure 25, the ADV7180 can decode a video signal as long as it fits into the ADC window. The components to this are the amplitude of the input signal and the dc level it resides on. The dc level is set by the clamping circuitry (see the Clamp Operation section). If the amplitude of the analog video signal is too high, clipping may occur, resulting in visual artifacts. The analog input range of the ADC, together with the clamp level, determines the maximum supported amplitude of the video signal. Figure 24 shows a typical voltage divider network that is required to keep the input video signal within the allowed range
Y/C
Dependent on horizontal sync depth Peak white
YPrPb
Dependent on horizontal sync depth
It is possible to freeze the automatic gain control loops. This causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed. The currently active gain from any of the modes can be read back. Refer to the description of the dual-function manual gain registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the Luma Gain and Chroma Gain sections.
ANALOG VOLTAGE RANGE SUPPORTED BY ADC (1V RANGE FOR ADV7180) MAXIMUM VOLTAGE
VIDEO PROCESSOR (GAIN SELECTION ONLY) ADC DATA PREPROCESSOR (DPP)
05700-025
GAIN CONTROL MINIMUM VOLTAGE CLAMP LEVEL
Figure 25. Gain Control Overview
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ADV7180
Luma Gain LAGC[2:0], Luma Automatic Gain Control, Address 0x2C [6:4]
The luma automatic gain control mode bits select the operating mode for the gain control in the luma path. There are internal parameters (Analog Devices proprietary algorithms) to customize the peak white gain control. Contact local Analog Devices field applications engineers or local Analog Devices distributor for more information. Table 35. LAGC Function
LAGC[2:0] 000 001 010 (default) 011 100 101 110 111 Description Manual fixed gain (use LMG[11:0]) Reserved AGC (blank level to sync tip), peak white algorithm on Reserved AGC (blank level to sync tip), peak white algorithm off Reserved Reserved Freeze gain
LG[11:0], Luma Gain, Address 0x2F [3:0], Address 0x30 [7:0]; LMG[11:0], Luma Manual Gain, Address 0x2F [3:0], Address 0x30 [7:0]
Luma gain [11:0] is a dual-function register. If all of these registers are written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC[2:0] mode is switched to manual fixed gain. Equation 1 shows how to calculate a desired gain. If read back, this register returns the current gain value. Depending on the setting in the LAGC[2:0] bits, the value is one of the following: * * Luma manual gain value (LAGC[2:0] set to luma manual gain mode) Luma automatic gain value (LAGC[2:0] set to any of the automatic modes)
Table 37. LG/LMG Function
LG[11:0]/LMG[11:0] LMG[11:0] = X LG[11:0] Read/Write Write Read Description Manual gain for luma path Actual used gain
LAGT[1:0], Luma Automatic Gain Timing, Address 0x2F [7:6]
The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control. Note that this register only has an effect if the LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic gain control modes). If peak white AGC is enabled and active (see the STATUS_1[7:0], Address 0x10 [7:0] section), the actual gain update speed is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the part leaves peak white AGC, LAGT becomes relevant again. The update speed for the peak white algorithm can be customized by the use of internal parameters. Contact Analog Devices local field engineers for more information. Table 36. LAGT Function
LAGT[1:0] 00 01 10 11 (default) Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive
Luma Gain (525i )
(1024 < LMG [11 : 0 ] 4095) 1410
0.72 K 2.9
Luma Gain (NTSC)
(1024 < LMG [11 : 0 ] 4095) 1470
1535
0.7 K 2.78
Luma Gain (PAL/625i)
(1024 < LMG[11 : 0 ] 4095)
0.66 K 2.66
(1) For example, with a 525i input applied, program the ADV7180 into manual fixed gain mode with a desired gain of 0.89 as follows: 1. 2. 3. 4. Use Equation 1 to convert the gain: 0.89 x 1410 = 1254.9 Truncate to integer value: = 1255d Convert to hexadecimal: 1255d = 0x04E7 Split into two registers and program: Luma Gain Control 1 [3:0] = 0x4 Luma Gain Control 2 [7:0] = 0xE7 Enable manual fixed gain mode: Set LAGC[2:0] to 000
5.
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ADV7180
BETACAM, Enable Betacam Levels, Address 0x01 [5]
If YPrPb data is routed through the ADV7180, the automatic gain control modes can target different video input levels, as outlined in Table 40. Note that the BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation. A review of the following sections is useful: * MAN_MUX_EN, Manual Input Muxing Enable, Address 0xC4 [7] for how component video (YPrPb) can be routed through the ADV7180. Video Standard Selection to select the various standards, for example, with and without pedestal.
PW_UPD, Peak White Update, Address 0x2B [0]
The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. LAGC[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place. For more information, refer to the LAGC[2:0], Luma Automatic Gain Control, Address 0x2C [6:4] section. Setting PW_UPD to 0 updates the gain once per video line. Setting PW_UPD to 1 (default) updates the gain once per field.
*
The automatic gain control (AGC) algorithms adjust the levels based on the setting of the BETACAM bit (see Table 38).
Chroma Gain CAGC[1:0], Chroma Automatic Gain Control, Address 0x2C [1:0]
The two bits of color automatic gain control mode select the basic mode of operation for automatic gain control in the chroma path.
Table 38. BETACAM Function
BETACAM 0 (default) Description Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE Assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant
1
Table 39. CAGC Function
CAGC[1:0] 00 01 10 (default) 11 Description Manual fixed gain (use CMG[11:0]) Use luma gain for chroma Automatic gain (based on color burst) Freeze chroma gain
Table 40. Betacam Levels
Name Y Pb and Pr Sync Depth Betacam (mV) 0 to 714 (incl. 7.5% pedestal) -467 to +467 286 Betacam Variant (mV) 0 to 714 -505 to +505 286 SMPTE (mV) 0 to 700 -350 to +350 300 MII (mV) 0 to 700 (incl. 7.5% pedestal) -324 to +324 300
Rev. A | Page 34 of 112
ADV7180
CAGT[1:0], Chroma Automatic Gain Timing, Address 0x2D [7:6]
The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain control. This register has an effect only if the CAGC[1:0] register is set to 10 (automatic gain).
Table 41. CAGT Function
CAGT[1:0] 00 01 10 11 (default) Description Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive
CKE, Color Kill Enable, Address 0x2B [6]
The color kill enable bit allows the optional color kill function to be switched on or off. For QAM-based video standards (PAL and NTSC) as well as FM-based systems (SECAM), the threshold for the color kill decision is selectable via the CKILLTHR[2:0] bits. If color kill is enabled and the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines, color processing is switched off (black and white output). To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. The color kill option only works for input signals with a modulated chroma part. For component input (YPrPb), there is no color kill. Setting CKE to 0 disables color kill. Setting CKE to 1 (default) enables color kill.
CG[11:0], Chroma Gain, Address 0x2D [3:0], Address 0x2E [7:0]; CMG[11:0], Chroma Manual Gain, Address 0x2D [3:0], Address 0x2E [7:0]
Chroma gain [11:0] is a dual-function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode is switched to manual fixed gain. Refer to Equation 2 for calculating a desired gain. If read back, this register returns the current gain value. Depending on the setting in the CAGC[1:0] bits, this is either: * * The chroma manual gain value (CAGC[1:0] set to chroma manual gain mode). The chroma automatic gain value (CAGC[1:0] set to any of the automatic modes).
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D [6:4]
The CKILLTHR[2:0] bits allow the user to select a threshold for the color kill function. The threshold applies to only QAMbased (NTSC and PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For Settings 000, 001, 010, and 011, chroma demodulation inside the ADV7180 may not work satisfactorily for poor input video signals.
Table 43. CKILLTHR Function
CKILLTHR[2:0] 000 001 010 011 (default) 100 101 110 111 Description SECAM NTSC, PAL No color kill Kill at <0.5% Kill at <5% Kill at <1.5% Kill at <7% Kill at <2.5% Kill at <8% Kill at <4.0% Kill at <9.5% Kill at <8.5% Kill at <15% Kill at <16.0% Kill at <32% Kill at <32.0% Reserved for Analog Devices internal use only. Do not select.
Table 42. CG/CMG Function
CG[11:0]/CMG[11:0] CMG[11:0] CG[11:0] Read/Write Write Read Description Manual gain for chroma path Currently active gain
Chroma_Gain
(0 < CG 4095) 650
0 . . . 6.29
(2)
For example, freezing the automatic gain loop and reading back the CG[11:0] register results in a value of 0x47A as follows: 1. 2. Convert the readback value to decimal: 0x47A = 1146d Apply Equation 2 to convert the readback value: 1146/1024 = 1.12
Rev. A | Page 35 of 112
ADV7180
CHROMA TRANSIENT IMPROVEMENT (CTI)
The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. The uneven bandwidth, however, may lead to visual artifacts in sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (see Figure 26). Due to the higher bandwidth, the signal transition of the luma component is usually much sharper than that of the chroma component. The color edge is not sharp and can be blurred, in the worst case, over several pixels.
CTI_AB_EN, Chroma Transient Improvement Alpha Blend Enable, Address 0x4D [1]
The CTI_AB_EN bit enables an alpha blend function within the CTI block. If set to 1, the alpha blender mixes the transient improved chroma with the original signal. The sharpness of the alpha blending can be configured via the CTI_AB[1:0] bits. For the alpha blender to be active, the CTI block must be enabled via the CTI_EN bit. Setting CTI_AB_EN to 0 disables the CTI alpha blender. Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend mixing function.
LUMA SIGNAL
LUMA SIGNAL WITH A TRANSITION, ACCOMPANIED BY A CHROMA TRANSITION
CTI_AB[1:0], Chroma Transient Improvement Alpha Blend, Address 0x4D [3:2]
The CTI_AB[1:0] controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one. It thereby controls the visual impact of CTI on the output data.
05700-026
DEMODULATED CHROMA SIGNAL
ORIGINAL, SLOW CHROMA TRANSITION PRIOR TO CTI SHARPENED CHROMA TRANSITION AT THE OUTPUT OF CTI
Figure 26. CTI Luma/Chroma Transition
For CTI_AB[1:0] to become active, the CTI block must be enabled via the CTI_EN bit and the alpha blender must be switched on via CTI_AB_EN. Sharp blending maximizes the effect of CTI on the picture, but may also increase the visual impact of small amplitude, high frequency chroma noise.
Table 44. CTI_AB Function
CTI_AB[1:0] 00 01 10 11 (default) Description Sharpest mixing between sharpened and original chroma signal Sharp mixing Smooth mixing Smoothest alpha blend function
The chroma transient improvement block examines the input video data. It detects transitions of chroma and can be programmed to create steeper chroma edges in an attempt to artificially restore lost color bandwidth. The CTI block, however, operates only on edges above a certain threshold to ensure that noise is not emphasized. Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided. Chroma transient improvements are needed primarily for signals that have severe chroma bandwidth limitations. For those types of signals, it is strongly recommended to enable the CTI block via CTI_EN.
CTI_EN, Chroma Transient Improvement Enable, Address 0x4D [0]
Setting CTI_EN to 0 disables the CTI block. Setting CTI_EN to 1 (default) enables the CTI block.
CTI_C_TH[7:0], CTI Chroma Threshold, Address 0x4E [7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number specifying how big the amplitude step in a chroma transition has to be in order to be steepened by the CTI block. Programming a small value into this register causes even smaller edges to be steepened by the CTI block. Making CTI_C_TH[7:0] a large value causes the block to improve large transitions only. The default value for CTI_C_TH[7:0] is 0x08, indicating the threshold for the chroma edges prior to CTI.
Rev. A | Page 36 of 112
ADV7180
DIGITAL NOISE REDUCTION (DNR) AND LUMA PEAKING FILTER
Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal, therefore, improves picture quality. There are two DNR blocks in the ADV7180: the DNR1 block before the luma peaking filter and the DNR2 block after the luma peaking filter, as shown in Figure 27.
PEAKING_GAIN[7:0], Luma Peaking Gain, Address 0xFB [7:0]
This filter can be manually enabled. The user can select to boost or attenuate the mid region of the Y spectrum around 3 MHz. The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz. The default value on this register passes through the luma data unaltered. A lower value attenuates the signal, and a higher value gains the luma signal. A plot of the filter's responses is shown in Figure 28.
Table 47. PEAKING_GAIN[7:0] Function
Setting 0x40 (Default)
15 10
LUMA SIGNAL
DNR1
LUMA PEAKING FILTER
DNR2
LUMA OUTPUT
05700-051
Description 0 dB response
PEAKING GAIN USING BP FILTER
Figure 27. DNR and Peaking Block Diagram
DNR_EN, Digital Noise Reduction Enable, Address 0x4D [5]
FILTER RESPONSE (dB)
The DNR_EN bit enables the DNR block or bypasses it.
Table 45. DNR_EN Function
Setting 0 1 (Default) Description Bypasses DNR (disable) Enables digital noise reduction on the luma data
5 0 -5 -10 -15
DNR_TH[7:0], DNR Noise Threshold, Address 0x50 [7:0]
The DNR1 block is positioned before the luma peaking block. The DNR_TH[7:0] value is an unsigned, 8-bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH[7:0] causes the DNR block to interpret even large transients as noise and remove them. As a result, the effect on the video data is more visible. Programming a small value causes only small transients to be seen as noise and to be removed.
Table 46. DNR_TH[7:0] Function
Setting 0x08 (Default) Description Threshold for maximum luma edges to be interpreted as noise
-20 0 1 2 3 4 FREQUENCY (MHz) 5 6 7
Figure 28. Peaking Filter Responses
DNR_TH2[7:0], DNR Noise Threshold 2, Address 0xFC [7:0]
The DNR2 block is positioned after the luma peaking block and, therefore, affects the gained luma signal. It operates in the same way as the DNR1 block, but there is an independent threshold control, DNR_TH2[7:0], for this block. This value is an unsigned, 8-bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH2[7:0] causes the DNR block to interpret even large transients as noise and remove them. As a result, the effect on the video data is more visible. Programming a small value causes only small transients to be seen as noise and to be removed.
Table 48. DNR_TH2[7:0] Function
Setting 0x04 (Default) Description Threshold for maximum luma edges to be interpreted as noise
Rev. A | Page 37 of 112
05700-052
ADV7180
COMB FILTERS
The comb filters of the ADV7180 have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the user to customize comb filter operation, depending on which video standard is detected (by autodetection) or selected (by manual programming). In addition to the bits listed in this section, there are some further internal controls (based on Analog Devices proprietary algorithms); contact local Analog Devices field engineers for more information.
NTSC Comb Filter Settings
Used for NTSC M/J CVBS inputs.
NSFSEL[1:0], Split Filter Selection NTSC, Address 0x19 [3:2]
The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection results in better performance on diagonal lines, but more dot crawl in the final output image. The opposite is true for selecting a wide bandwidth split filter.
Table 49. NSFSEL Function
NSFSEL[1:0] 00 (default) 01 10 11 Description Narrow Medium Medium Wide
CTAPSN[1:0] Chroma Comb Taps NTSC, Address 0x38 [7:6]
Table 50. CTAPSN Function
CTAPSN[1:0] 00 01 10 (default) 11 Description Do not use NTSC chroma comb adapts three lines (three taps) to two lines (two taps) NTSC chroma comb adapts five lines (five taps) to three lines (three taps) NTSC chroma comb adapts five lines (five taps) to four lines (four taps)
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3]
Table 51. CCMN Function
CCMN[2:0] 0xx (default) Description Adaptive comb mode Configuration Adaptive 3-line chroma comb for CTAPSN = 01 Adaptive 4-line chroma comb for CTAPSN = 10 Adaptive 5-line chroma comb for CTAPSN = 11 Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11 Fixed 3-line chroma comb for CTAPSN = 01 Fixed 4-line chroma comb for CTAPSN = 10 Fixed 5-line chroma comb for CTAPSN = 11 Fixed 2-line chroma comb for CTAPSN = 01 Fixed 3-line chroma comb for CTAPSN = 10 Fixed 4-line chroma comb for CTAPSN = 11
100 101
Disable chroma comb Fixed chroma comb (top lines of line memory)
110
Fixed chroma comb (all lines of line memory)
111
Fixed chroma comb (bottom lines of line memory)
Rev. A | Page 38 of 112
ADV7180
YCMN[2:0], Luma Comb Mode NTSC, Address 0x38 [2:0]
Table 52. YCMN Function
YCMN[2:0] 0xx (default) 100 Description Adaptive comb mode Disable luma comb Configuration Adaptive 3-line (three taps) luma comb Use low-pass/notch filter; see the Y Shaping Filter section Fixed 2-line (two taps) luma comb Fixed 3-line (three taps) luma comb Fixed 2-line (two taps) luma comb
CCMP[2:0], Chroma Comb Mode PAL, Address 0x39 [5:3]
Table 55. CCMP Function
CCMP[2:0] 0xx (default) Description Adaptive comb mode Configuration Adaptive 3-line chroma comb for CTAPSP = 01 Adaptive 4-line chroma comb for CTAPSP = 10 Adaptive 5-line chroma comb for CTAPSP = 11
101 110 111
Fixed luma comb (top lines of line memory) Fixed luma comb (all lines of line memory) Fixed luma comb (bottom lines of line memory)
100 101
Disable chroma comb Fixed chroma comb (top lines of line memory)
PAL Comb Filter Settings
Used for PAL B/G/H/I/D, PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS inputs.
110 Fixed chroma comb (all lines of line memory)
PSFSEL[1:0], Split Filter Selection PAL, Address 0x19 [1:0]
The PSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A wide split filter selection eliminates dot crawl, but shows imperfections on diagonal lines. The opposite is true for selecting a narrow bandwidth split filter.
Table 53. PSFSEL Function
PSFSEL[1:0] 00 01 (default) 10 11 Description Narrow Medium Wide Widest
111
Fixed chroma comb (bottom lines of line memory)
Fixed 2-line chroma comb for CTAPSP = 01 Fixed 3-line chroma comb for CTAPSP = 10 Fixed 4-line chroma comb for CTAPSP = 11 Fixed 3-line chroma comb for CTAPSP = 01 Fixed 4-line chroma comb for CTAPSP = 10 Fixed 5-line chroma comb for CTAPSP = 11 Fixed 2-line chroma comb for CTAPSP = 01 Fixed 3-line chroma comb for CTAPSP = 10 Fixed 4-line chroma comb for CTAPSP = 11
YCMP[2:0], Luma Comb Mode PAL, Address 0x39 [2:0]
Table 56. YCMP Function
YCMP[2:0] 0xx (default) 100 Description Adaptive comb mode Disable luma comb Configuration Adaptive five lines (three taps) luma comb Use low-pass/notch filter; see the Y Shaping Filter section. Fixed three lines (two taps) luma comb Fixed five lines (three taps) luma comb Fixed three lines (two taps) luma comb
CTAPSP[1:0], Chroma Comb Taps PAL, Address 0x39 [7:6]
Table 54. CTAPSP Function
CTAPSP[1:0] 00 01 10 Description Do not use PAL chroma comb adapts five lines (three taps) to three lines (two taps); cancels cross luma only PAL chroma comb adapts five lines (five taps) to three lines (three taps); cancels cross luma and hue error less well PAL chroma comb adapts five lines (five taps) to four lines (four taps); cancels cross luma and hue error well
101
110
11 (default)
111
Fixed luma comb (top lines of line memory) Fixed luma comb (all lines of line memory) Fixed luma comb (bottom lines of line memory)
Rev. A | Page 39 of 112
ADV7180
IF FILTER COMPENSATION
IFFILTSEL[2:0], IF Filter Select, Address 0xF8 [2:0]
The IFFILTSEL[2:0] register allows the user to compensate for SAW filter characteristics on a composite input, as would be observed on tuner outputs. Figure 29 and Figure 30 show IF filter compensation for NTSC and PAL, respectively. The options for this feature are as follows: * * * Bypass mode NTSC--consists of three filter characteristics PAL--consists of three filter characteristics
6 4 2
AMPLITUDE (dB)
IF COMP FILTERS NTSC ZOOMED AROUND FSC
0 -2 -4 -6 -8 -10 -12 2.0
05700-053
See Table 103 for programming details.
2.5
3.0 3.5 4.0 FREQUENCY (MHz)
4.5
5.0
Figure 29. NTSC IF Filter Compensation
6 4 2
AMPLITUDE (dB)
IF COMP FILTERS PAL ZOOMED AROUND FSC
0 -2 -4 -6 -8 3.0
3.5
4.0 4.5 5.0 FREQUENCY (MHz)
5.5
6.0
Figure 30. PAL IF Filter Compensation
Rev. A | Page 40 of 112
05700-054
ADV7180
AV CODE INSERTION AND CONTROLS
This section describes the I2C-based controls that affect * * * * Insertion of AV codes into the data stream Data blanking during the vertical blank interval (VBI) The range of data values permitted in the output data stream The relative delay of luma vs. chroma signals In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00, and Y = AV. In a 16-bit output interface (ADV7180 LQFP-64 only) where Y and Cr/Cb are delivered via separate data buses, the AV code is spread over the whole 16 bits. The SD_DUP_AV bit allows the user to replicate the AV codes on both buses, so the full AV sequence can be found on the Y bus as well as on the Cr/Cb bus (see Figure 31). When SD_DUP_AV is 0 (default), the AV codes are in single fashion (to suit 8-bit interleaved data output). When SD_DUP_AV is 1, the AV codes are duplicated (for 16-bit interfaces).
Note that some of the decoded VBI data is inserted during the horizontal blanking interval. See the Gemstar Data Recovery section for more information.
BT.656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]
Between Revision 3 and Revision 4 of the ITU-R BT.656 standards, the ITU has changed the toggling position for the V bit within the SAV EAV codes for NTSC. The ITU-R BT.656-4 standard bit allows the user to select an output mode that is compliant with either the previous or new standard. For further information, visit the International Telecommunication Union's website. Note that the standard change only affects NTSC and has no bearing on PAL. When ITU-R BT.656-4 is 0 (default), the ITU-R BT.656-3 specification is used. The V bit goes low at EAV of Line 10 and Line 273. When ITU-R BT.656-4 is 1, the ITU-R BT.656-4 specification is used. The V bit goes low at EAV of Line 20 and Line 283.
VBI_EN, Vertical Blanking Interval Data Enable, Address 0x03 [7]
The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering. All data for Line 1 to Line 21 is passed through and available at the output port. The ADV7180 does not blank the luma data and automatically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored. See the BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2] section for information on the chroma path. When VBI_EN is 0 (default), all video lines are filtered/scaled. When VBI_EN is 1, only the active video region is filtered/scaled.
SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]
Depending on the output interface width, it may be necessary to duplicate the AV codes from the luma path into the chroma path. In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as FF/00/00/AV, with AV being the transmitted word that contains information about H/V/F.
SD_DUP_AV = 1 16-BIT INTERFACE Y DATA BUS FF 00 00 AV Y
SD_DUP_AV = 0 16-BIT INTERFACE 00 AV Y Cb/Y/Cr/Y INTERLEAVED FF 00 00 AV Cb
05700-027
8-BIT INTERFACE
Cr/Cb DATA BUS
FF
00
00
AV
Cb
FF
00
Cb AV CODE SECTION
AV CODE SECTION
AV CODE SECTION
Figure 31. AV Code Duplication Control (ADV7180 LQFP-64 Only)
Rev. A | Page 41 of 112
ADV7180
BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]
Setting BL_C_VBI high, blanks the Cr and Cb values of all VBI lines. This is done so any data that may arrive during VBI is not decoded as color and is output through Cr and Cb. As a result, it is possible to send VBI lines into the decoder, and then output them through an encoder again, undistorted. Without this blanking, any color that is incorrectly decoded would be encoded by the video encoder, thus distorting the VBI lines. Setting BL_C_VBI to 0 decodes and outputs color during VBI. Setting BL_C_VBI to 1 (default) blanks Cr and Cb values during VBI. When AUTO_PDC_EN is 1 (default), the ADV7180 automatically determines the LTA and CTA values to have luma and chroma aligned at the output.
LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0]
The luma timing adjust register allows the user to specify a timing difference between chroma and luma samples. Note that there is a certain functionality overlap with the CTA[2:0] register. For manual programming, use the following defaults: * * * CVBS input LTA[1:0] = 00 Y/C input LTA[1:0] = 01 YPrPb input LTA[1:0] = 01
RANGE, Range Selection, Address 0x04 [0]
AV codes (as per ITU-R BT.656, formerly known as CCIR-656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore are not to be used for active video. Additionally, the ITU specifies that the nominal range for video should be restricted to values between 16 to 235 for luma and 16 to 240 for chroma. The RANGE bit allows the user to limit the range of values output by the ADV7180 to the recommended value range. In any case, it ensures that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part of an AV code header.
Table 57. RANGE Function
RANGE 0 1 (default) Description 16 Y 235 1 Y 254 16 C/P 240 1 C/P 254
Table 58. LTA Function
LTA[1:0] 00 (default) 01 10 11 Description No delay Luma 1 clock (37 ns) late Luma 2 clock (74 ns) early Luma 1 clock (37 ns) early
CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3]
The chroma timing adjust register allows the user to specify a timing difference between chroma and luma samples. This may be used to compensate for external filter group delay differences in the luma vs. chroma path and to allow a different number of pipeline delays while processing the video downstream. Review this functionality together with the LTA[1:0] register. The chroma can be delayed or advanced only in chroma pixel steps. One chroma pixel step is equal to two luma pixels. The programmable delay occurs after demodulation, where one can no longer delay by luma pixel steps. For manual programming, use the following defaults: * * * CVBS input CTA[2:0] = 011 Y/C input CTA[2:0] = 101 YPrPb input CTA[2:0] = 110
AUTO_PDC_EN, Automatic Programmed Delay Control, Address 0x27 [6]
Enabling AUTO_PDC_EN activates a function within the ADV7180 that automatically programs the LTA[1:0] and CTA[2:0] to have the chroma and luma data match delays for all modes of operation. If set, manual registers LTA[1:0] and CTA[2:0] are not used. If the automatic mode is disabled (by setting the AUTO_PDC_EN bit to 0), the values programmed into LTA[1:0] and CTA[2:0] registers become active. When AUTO_PDC_EN is 0, the ADV7180 uses the LTA[1:0] and CTA[2:0] values for delaying luma and chroma samples. Refer to the LTA[1:0], Luma Timing Adjust, Address 0x27 [1:0] section and the CTA[2:0], Chroma Timing Adjust, Address 0x27 [5:3] section.
Table 59. CTA Function
CTA[2:0] 000 001 010 011 (default) 100 101 110 111 Description Not used Chroma + 2 chroma pixel (early) Chroma + 1 chroma pixel (early) No delay Chroma - 1 chroma pixel (late) Chroma - 2 chroma pixel (late) Chroma - 3 chroma pixel (late) Not used
Rev. A | Page 42 of 112
ADV7180
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The following controls allow the user to configure the behavior of the HS output pin only: * * * Beginning of HS signal via HSB[10:0] End of HS signal via HSE[10:0] Polarity of HS using PHS
HSE[10:0], HS End, Address 0x34 [2:0], Address 0x36 [7:0]
The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see Figure 32). HSE is set to 00000000000b, which is 0 LLC1 clock cycles from count [0]. The default value of HSE[10:0] is 000, indicating that the HS pulse ends 0 pixels after the falling edge of HS. For example, * To shift the HS toward active video by 20 LLC1s, add 20 LLC1s to both HSB and HSE--that is, HSB[10:0] = [00000010110], HSE[10:0] = [00000010100]. To shift the HS away from active video by 20 LLC1s, add 1696 LLC1s to both HSB and HSE (for NTSC)--that is, HSB[10:0] = [11010100010], HSE[10:0] = [11010100000]. Therefore, 1696 is derived from the NTSC total number of pixels, 1716. To move 20 LLC1s away from active video, subtract 20 from 1716 and add the result in binary to both HSB[10:0] and HSE[10:0].
The HS begin (HSB) and HS end (HSE) registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and length of the HS output signal.
HSB[10:0], HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The position of this edge is controlled by placing a binary number into HSB[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see Figure 32). HSB is set to 00000000010b, which is two LLC1 clock cycles from count [0]. The default value of HSB[10:0] is 0x002, indicating that the HS pulse starts two pixels after the falling edge of HS.
*
*
PHS, Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit. When PHS is 0 (default), HS is active high. When PHS is 1, HS is active low.
Table 60. HS Timing Parameters (See Figure 32)
Characteristic HS to Active Video LLC1 Clock Cycles, C in Figure 32 (Default) 272 276 284 Active Video Samples/Line, D in Figure 32 720Y + 720C = 1440 640Y + 640C = 1280 720Y + 720C = 1440 Total LLC1 Clock Cycles, E in Figure 32 1716 1560 1728
Standard NTSC NTSC Square Pixel PAL
HS Begin Adjust HSB[10:0] (Default) 00000000010b 00000000010b 00000000010b
HS End Adjust HSE[10:0] (Default) 00000000000b 00000000000b 00000000000b
Figure 32. HS Timing
Rev. A | Page 43 of 112
ADV7180
VS and FIELD Configuration
The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes. Note that the ADV7180 LQFP-64 has separate VS and FIELD pins. The ADV7180 LFCSP-40 does not have separate VS and FIELD pins, but can output either one on Pin 37, the VS/FIELD pin.
HVSTIM, Horizontal VS Timing, Address 0x31 [3]
The HVSTIM bit allows the user to select where the VS signal is asserted within a line of video. Some interface circuitry may require VS to go low while HS is low. When HVSTIM is 0 (default), the start of the line is relative to HSE. When HVSTIM is 1, the start of the line is relative to HSB.
VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]
VSYNC/FIELD SELECT, Address 0x58 [0]
This feature is used for the ADV7180 LFCSP-40 (ADV7180BCPZ) only. The polarity of this bit determines what signal appears on the VS/FIELD pin. When this bit is set to 0 (default), the FIELD signal is output. When this bit is set to 1, the VSYNC signal is output. The ADV7180 LQFP-64 (ADV7180BSTZ) has dedicated FIELD and VSYNC pins. ADV encoder-compatible signals via NEWAVMODE are * * * * PVS, PF HVSTIM VSBHO, VSBHE VSEHO, VSEHE
The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low. When VSBHO is 0 (default), the VS pin goes high at the middle of a line of video (odd field). When VSBHO is 1, the VS pin changes state at the start of a line (odd field).
VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]
The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to only change state when HS is high/low. When VSBHE is 0 (default), the VS pin goes high at the middle of a line of video (even field). When VSBHE is 1, the VS pin changes state at the start of a line (even field).
VSEHO, VS End Horizontal Position Odd, Address 0x33 [7]
For NTSC control, * * * NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0] NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0] NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0]
For PAL control, * * * PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0] PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0] PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0]
The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low. When VSEHO is 0 (default), the VS pin goes low (inactive) at the middle of a line of video (odd field). When VSEHO is 1, the VS pin changes state at the start of a line (odd field).
VSEHE, VS End Horizontal Position Even, Address 0x33 [6]
NEWAVMODE, New AV Mode, Address 0x31 [4]
When NEWAVMODE is 0, EAV/SAV codes are generated to suit Analog Devices encoders. No adjustments are possible. Setting NEWAVMODE to 1 (default) enables the manual position of the VSYNC, FIELD, and AV codes using Register 0x34 to Register 0x37 and Register 0xE5 to Register 0xEA. Default register settings are CCIR656 compliant; see Figure 33 for NTSC and Figure 38 for PAL. For recommended manual user settings, see Table 61 and Figure 34 for NTSC and Table 62 and Figure 39 for PAL.
The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to only change state when HS is high/low. When VSEHE is 0 (default), the VS pin goes low (inactive) at the middle of a line of video (even field). When VSEHE is 1, the VS pin changes state at the start of a line (even field).
Rev. A | Page 44 of 112
ADV7180
PVS, Polarity VS, Address 0x37 [5] The polarity of the VS pin can be inverted using the PVS bit. Table 61. User Settings for NTSC (See Figure 34)
Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE5 0xE6 0xE7 Register Name VS/FIELD Control 1 VS/FIELD Control 2 VS/FIELD Control 3 HS Position Control 1 HS Position Control 2 HS Position Control 3 Polarity NTSV V Bit Begin NTSC V Bit End NTSC F Bit Toggle Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 0x41 0x84 0x06
When PVS is 0 (default), VS is active high. When PVS is 1, VS is active low.
PF, Polarity FIELD, Address 0x37 [3] The polarity of the FIELD pin can be inverted using the PF bit. The FIELD pin can be inverted using the PF bit. When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
FIELD 1 525 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 FIELD 2 262 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3
1APPLIES IF NEWAVMODE = 0:
05700-029
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
NVEND[4:0] = 0x4
1BT.656-4
REG 0x04, BIT 7 = 1
263
264
265
266
267
268
269
270
271
272
273
274
275
276
283
284
285
NVEND[4:0] = 0x4
1BT.656-4
REG 0x04, BIT 7 = 1
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 33. NTSC Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
FIELD 1 525 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT FIELD 2 262 OUTPUT VIDEO HS OUTPUT VS OUTPUT NVBEG[4:0] = 0x0 FIELD OUTPUT NVEND[4:0] = 0x3
05700-030
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3 NFTOG[4:0] = 0x5
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
284
285
NFTOG[4:0] = 0x5
Figure 34. NTSC Typical VSYNC/FIELD Positions Using Register Writes in Table 61
Rev. A | Page 45 of 112
ADV7180
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field, Address 0xE5 [7]
When NVBEGDELO is 0 (default), there is no delay. Setting NVBEGDELO to 1 delays VSYNC going high on an odd field by a line relative to NVBEG.
1 NVBEGSIGN 0 1 NVENDSIGN 0
For all NTSC/PAL VSYNC timing controls, both the V bit in the AV code and the VSYNC on the VS pin are modified.
ADVANCE END OF VSYNC BY NVEND[4:0]
DELAY END OF VSYNC BY NVEND[4:0]
ADVANCE BEGIN OF VSYNC BY NVBEG[4:0]
DELAY BEGIN OF VSYNC BY NVBEG[4:0]
NOT VALID FOR USER PROGRAMMING ODD FIELD?
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
YES
NO
NVENDDELO
NVENDDELE
NVBEGDELO
NVBEGDELE
1
0
0
1
1
0
0
1
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE VSEHO VSEHE
VSBHO
VSBHE
1
0
0
1
1
0
0
1
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
VSYNC END
05700-031
Figure 36. NTSC Vsync End
VSYNC BEGIN
Figure 35. NTSC Vsync Begin
NVENDDELO, NTSC Vsync End Delay on Odd Field, Address 0xE6 [7]
When NVENDDELO is 0 (default), there is no delay. Setting NVENDDELO to 1 delays vsync from going low on an odd field by a line relative to NVEND.
NVBEGDELE, NTSC Vsync Begin Delay on Even Field, Address 0xE5 [6]
When NVBEGDELE is 0 (default), there is no delay. Setting NVBEGDELE to 1 delays vsync going high on an even field by a line relative to NVBEG.
NVENDDELE, NTSC Vsync End Delay on Even Field, Address 0xE6 [6]
When NVENDDELE is set to 0 (default), there is no delay. Setting NVENDDELE to 1 delays vsync from going low on an even field by a line relative to NVEND.
NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
Setting NVBEGSIGN to 0 delays the start of vsync. Set for user manual programming. Setting NVBEGSIGN to 1 (default) advances the start of vsync. Not recommended for user programming.
NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
Setting NVENDSIGN to 0 (default) delays the end of vsync. Set for user manual programming. Setting NVENDSIGN to 1 advances the end of vsync. Not recommended for user programming.
NVBEG[4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
The default value of NVBEG is 00101, indicating the NTSC vsync begin position.
Rev. A | Page 46 of 112
05700-032
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
ADV7180
NVEND[4:0], NTSC Vsync End, Address 0xE6 [4:0]
The default value of NVEND is 00100, indicating the NTSC vsync end position. For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified.
NFTOG[4:0], NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC field toggle position. For all NTSC/PAL field timing controls, both the F bit in the AV code and the field signal on the FIELD/DE pin are modified.
1 NFTOGSIGN 0
NFTOGDELO, NTSC FIELD Toggle Delay on Odd Field, Address 0xE7 [7]
When NFTOGDELO is 0 (default), there is no delay. Setting NFTOGDELO to 1 delays the field toggle/transition on an odd field by a line relative to NFTOG.
ADVANCE TOGGLE OF FIELD BY NFTOG[4:0]
DELAY TOGGLE OF FIELD BY NFTOG[4:0]
NFTOGDELE, NTSC Field Toggle Delay on Even Field, Address 0xE7 [6]
When NFTOGDELE is 0, there is no delay. Setting NFTOGDELE to 1 (default) delays the field toggle/ transition on an even field by a line relative to NFTOG.
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
NFTOGDELO
NFTOGDELE
NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
Setting NFTOGSIGN to 0 delays the field transition. Set for user manual programming. Setting NFTOGSIGN to 1 (default) advances the field transition. Not recommended for user programming.
1
0
0
1
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
FIELD TOGGLE
Figure 37. NTSC FIELD Toggle
FIELD 1 OUTPUT VIDEO H 622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24
V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 FIELD 2 310 OUTPUT VIDEO H 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 PVEND[4:0] = 0x4
V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 PVEND[4:0] = 0x4
05700-034
Figure 38. PAL Default, ITU-R BT.656 (the Polarity of H, V, and F is Embedded in the Data)
Rev. A | Page 47 of 112
05700-033
ADV7180
FIELD 1 622 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT FIELD 2 310 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVBEG[4:0] = 0x1 FIELD OUTPUT PVEND[4:0] = 0x4
05700-035
623
624
625
1
2
3
4
5
6
7
8
9
10
11
23
24
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4 PFTOG[4:0] = 0x6
311
312
313
314
315
316
317
318
319
320
321
322
323
336
337
PFTOG[4:0] = 0x6
Figure 39. PAL Typical VS/FIELD Positions Using Register Writes Shown in Table 62
Table 62. User Settings for PAL
Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE8 0xE9 0xEA Register Name VS/FIELD Control 1 VS/FIELD Control 2 VS/FIELD Control 3 HS Position Control 1 HS Position Control 2 HS Position Control 3 Polarity PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 0x41 0x84 0x06
PVBEG[4:0], PAL Vsync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL vsync begin position. For all NTSC/PAL vsync timing controls, the V bit in the AV code and the vsync on the VS pin are modified.
1 PVBEGSIGN 0
ADVANCE BEGIN OF VSYNC BY PVBEG[4:0]
DELAY BEGIN OF VSYNC BY PVBEG[4:0]
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
PVBEGDELO, PAL Vsync Begin Delay on Odd Field, Address 0xE8 [7]
When PVBEGDELO is 0 (default), there is no delay. Setting PVBEGDELO to 1 delays vsync going high on an odd field by a line relative to PVBEG.
PVBEGDELO
PVBEGDELE
1
0
0
1
PVBEGDELE PAL, Vsync Begin Delay on Even Field, Address 0xE8 [6]
When PVBEGDELE is 0, there is no delay. Setting PVBEGDELE to 1 (default) delays vsync going high on an even field by a line relative to PVBEG.
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
VSBHO
VSBHE
1
0
0
1
PVBEGSIGN PAL, Vsync Begin Sign, Address 0xE8 [5]
Setting PVBEGSIGN to 0 delays the beginning of vsync. Set for user manual programming. Setting PVBEGSIGN to 1(default) advances the beginning of vsync. Not recommended for user programming.
ADVANCE BY 0.5 LINE ADVANCE BY 0.5 LINE
VSYNC BEGIN
Figure 40. PAL Vsync Begin
Rev. A | Page 48 of 112
05700-036
ADV7180
1 PVENDSIGN 0
PFTOGDELO, PAL Field Toggle Delay on Odd Field, Address 0xEA [7]
When PFTOGDELO is 0 (default), there is no delay. Setting PFTOGDELO to 1 delays the F toggle/transition on an odd field by a line relative to PFTOG.
ADVANCE END OF VSYNC BY PVEND[4:0]
DELAY END OF VSYNC BY PVEND[4:0]
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
PFTOGDELE, PAL Field Toggle Delay on Even Field, Address 0xEA [6]
When PFTOGDELE is 0, there is no delay. Setting PFTOGDELE to 1 (default) delays the F toggle/transition on an even field by a line relative to PFTOG.
PVENDDELO
PVENDDELE
1
0
0
1
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
Setting PFTOGSIGN to 0 delays the field transition. Set for user manual programming. Setting PFTOGSIGN to 1 (default) advances the field transition. Not recommended for user programming.
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
PFTOG, PAL Field Toggle, Address 0xEA [4:0]
VSEHO VSEHE 1 0 0 1
The default value of PFTOG is 00011, indicating the PAL field toggle position. For all NTSC/PAL field timing controls, the F bit in the AV code and the field signal on the FIELD/DE pin are modified.
1 PFTOGSIGN 0
ADVANCE BY 0.5 LINE
ADVANCE BY 0.5 LINE
VSYNC END
05700-037
Figure 41. PAL Vsync End
ADVANCE TOGGLE OF FIELD BY PFTOG[4:0]
DELAY TOGGLE OF FIELD BY PFTOG[4:0]
PVENDDELO, PAL Vsync End Delay on Odd Field, Address 0xE9 [7]
When PVENDDELO is 0 (default), there is no delay. Setting PVENDDELO to 1 delays vsync going low on an odd field by a line relative to PVEND.
NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NO
PVENDDELE, PAL Vsync End Delay on Even Field, Address 0xE9 [6]
When PVENDDELE is 0 (default), there is no delay. Setting PVENDDELE to 1 delays vsync going low on an even field by a line relative to PVEND.
PFTOGDELO
PFTOGDELE
1
0
0
1
ADDITIONAL DELAY BY 1 LINE
ADDITIONAL DELAY BY 1 LINE
PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
Setting PVENDSIGN to 0 (default) delays the end of vsync. Set for user manual programming. Setting PVENDSIGN to 1 advances the end of vsync. Not recommended for user programming.
FIELD TOGGLE
05700-038
Figure 42. PAL F Toggle
PVEND[4:0], PAL Vsync End, Address 0xE9 [4:0]
The default value of PVEND is 10100, indicating the PAL vsync end position. For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified.
Rev. A | Page 49 of 112
ADV7180
SYNC PROCESSING
The ADV7180 has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I2C bits.
Table 64. NTSC
Feature Teletext System B and D Teletext System C/NABTS Vertical Interval Time Codes (VITC ) Copy Generation Management System (CGMS) Gemstar Closed Captioning (CCAP) Standard ITU-R BT.653 ITU-R BT.653/EIA-516 - EIA-J CPR-1204/IEC 61880 - EIA-608
ENHSPLL, Enable Hsync Processor, Address 0x01 [6]
The HSYNC processor is designed to filter incoming hsyncs that have been corrupted by noise, providing improved performance for video signals with stable time bases but poor SNR. Setting ENHSPLL to 0 disables the hsync processor. Setting ENHSPLL to 1 (default) enables the hsync processor.
ENVSPROC, Enable Vsync Processor, Address 0x01 [3]
This block provides extra filtering of the detected vsyncs to improve vertical lock. Setting ENVSPROC to 0 disables the vsync processor. Setting ENVSPROC to 1(default) enables the vsync processor.
The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default as described in Table 65. This can be overridden manually and any VBI data can be decoded on any line. The details of manual programming are described in Table 66.
VDP Default Configuration
The VDP can decode different VBI data standards on a line-toline basis. The various standards supported by default on different lines of VBI are explained in Table 65.
VBI DATA DECODE
There are two VBI data slicers on the ADV7180. The first is called the VBI data processor (VDP), and the second is called VBI System 2. The VDP can slice both low bandwidth standards and high bandwidth standards such as teletext. VBI System 2 can slice low data rate VBI standards only. The VDP is capable of slicing multiple VBI data standards on SD video. It decodes the VBI data on the incoming CVBS and Y/C or YUV data. The decoded results are available as ancillary data in output 656 data stream. For low data rate VBI standards like CC/WSS/CGMS, users can read the decoded data bytes from I2C registers. The VBI data standards that can be decoded by the VDP are listed in Table 63 and Table 64.
Table 63. PAL
Feature Teletext System A, C, or D Teletext System B/WST Video Programming System (VPS) Vertical Interval Time Codes ( VITC) Wide Screen Signaling (WSS) Closed Captioning (CCAP) Standard ITU-R BT.653 ITU-R BT.653 ETSI EN 300 231 V 1.3.1 - ITU-R BT.1119-1/ ETSI EN.300294 -
VDP Manual Configuration MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map
The user can configure the VDP to decode different standards on a line-to-line basis through manual line programming. For this, the user has to set the MAN_LINE_PGM bit. The user needs to write into all the line programming registers VBI_DATA_Px_Ny (see Register 0x64 to Register 0x77 in Table 104). 0 (default)--The VDP decodes default standards on lines, as shown in Table 65. 1--VBI standards to be decoded are manually programmed.
VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on Line X for PAL, Line Y for NTSC, Addresses 0x64 to 0x77, User Sub Map
These are related 4-bit clusters in Register 0x64 to Register 0x77 of the User Sub Map. These 4-bit, line programming registers, named VBI_DATA_Px_Ny, identify the VBI data standard that would be decoded on Line X in PAL or on Line Y in NTSC mode. The different types of VBI standards decoded by VBI_DATA_Px_Ny are shown in Table 66. Note that the X or Y value depends on whether the ADV7180 is in PAL or NTSC mode.
Rev. A | Page 50 of 112
ADV7180
Table 65. Default Standards on Lines for PAL and NTSC
PAL--625/50 Default VBI DATA Decoded Line No. WST 318 WST 319 WST 320 WST 321 WST 322 WST 323 WST 324 WST 325 WST 326 WST 327 VPS 328 329 330 VITC 331 WST 332 WST 333 CCAP 334 WSS 335 WST 336 337 + full even field Default VBI DATA Decoded VPS WST WST WST WST WST WST WST WST WST WST VPS VITC WST WST CCAP WST WST NTSC--525/60 Default VBI Line No. DATA Decoded Gemstar_1x - Gemstar_1x 286 Gemstar_1x 287 - 288 - - - - NABTS 272 NABTS 273 NABTS 274 NABTS 275 VITC 276 NABTS 277 VITC 278 NABTS 279 NABTS 280 NABTS 281 CGMS 282 CCAP 283 NABTS 284 285 + full even field Default VBI DATA Decoded - Gemstar_1x Gemstar_1x Gemstar_1x - - NABTS NABTS NABTS NABTS NABTS VITC NABTS VITC NABTS NABTS NABTS CGMS CCAP NABTS
Line No. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 + full odd field
Line No. 23 24 25 - - - 10 11 12 13 14 15 16 17 18 19 20 21 22 + full odd field
Table 66. VBI Data Standards for Manual Configuration
VBI_DATA_Px_Ny 0000 0001 0010 0011 0100 0101 0110 0111 1000 to 1111 625/50--PAL Disable VDP Teletext system identified by VDP_TTXT_TYPE VPS - ETSI EN 300 231 V 1.3.1 VITC WSS ITU-R BT.1119-1/ETSI.EN.300294 Reserved Reserved CCAP Reserved 525/60--NTSC Disable VDP Teletext system identified by VDP_TTXT_TYPE Reserved VITC CGMS EIA-J CPR-1204/IEC 61880 Gemstar_1x Gemstar_2x CCAP EIA-608 Reserved
Rev. A | Page 51 of 112
ADV7180
Table 67.VBI Data Standards to be Decoded on Line Px (PAL) or Line Ny (NTSC)
Signal Name VBI_DATA_P6_N23 VBI_DATA_P7_N24 VBI_DATA_P8_N25 VBI_DATA_P9 VBI_DATA_P10 VBI_DATA_P11 VBI_DATA_P12_N10 VBI_DATA_P13_N11 VBI_DATA_P14_N12 VBI_DATA_P15_N13 VBI_DATA_P16_N14 VBI_DATA_P17_N15 VBI_DATA_P18_N16 VBI_DATA_P19_N17 VBI_DATA_P20_N18 VBI_DATA_P21_N19 VBI_DATA_P22_N20 VBI_DATA_P23_N21 VBI_DATA_P24_N22 VBI_DATA_P318 VBI_DATA_P319_N286 VBI_DATA_P320_N287 VBI_DATA_P321_N288 VBI_DATA_P322 VBI_DATA_P323 VBI_DATA_P324_N272 VBI_DATA_P325_N273 VBI_DATA_P326_N274 VBI_DATA_P327_N275 VBI_DATA_P328_N276 VBI_DATA_P329_N277 VBI_DATA_P330_N278 VBI_DATA_P331_N279 VBI_DATA_P332_N280 VBI_DATA_P333_N281 VBI_DATA_P334_N282 VBI_DATA_P335_N283 VBI_DATA_P336_N284 VBI_DATA_P337_N285 Register Location VDP_LINE_00F[7:4] VDP_LINE_010[7:4] VDP_LINE_011[7:4] VDP_LINE_012[7:4] VDP_LINE_013[7:4] VDP_LINE_014[7:4] VDP_LINE_015[7:4] VDP_LINE_016[7:4] VDP_LINE_017[7:4] VDP_LINE_018[7:4] VDP_LINE_019[7:4] VDP_LINE_01A[7:4] VDP_LINE_01B[7:4] VDP_LINE_01C[7:4] VDP_LINE_01D[7:4] VDP_LINE_01E[7:4] VDP_LINE_01F[7:4] VDP_LINE_020[7:4] VDP_LINE_021[7:4] VDP_LINE_00E[3:0] VDP_LINE_00F[3:0] VDP_LINE_010[3:0] VDP_LINE_011[3:0] VDP_LINE_012[3:0] VDP_LINE_013[3:0] VDP_LINE_014[3:0] VDP_LINE_015[3:0] VDP_LINE_016[3:0] VDP_LINE_017[3:0] VDP_LINE_018[3:0] VDP_LINE_019[3:0] VDP_LINE_01A[3:0] VDP_LINE_01B[3:0] VDP_LINE_01C[3:0] VDP_LINE_01D[3:0] VDP_LINE_01E[3:0] VDP_LINE_01F[3:0] VDP_LINE_020[3:0] VDP_LINE_021[3:0] Dec Address 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Hex Address 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77
Note that full field detection (lines other than VBI lines) of any standard can also be enabled by writing into the registers VBI_DATA_P24_N22[3:0] and VBI_DATA_P337_N285[3:0]. So, if VBI_DATA_P24_N22[3:0] is programmed with any teletext standard, then teletext is decoded off for the entire odd field. The corresponding register for the even field is VBI_DATA_P337_N285[3:0]. For teletext system identification, VDP assumes that if teletext is present in a video channel, all the teletext lines comply with a single standard system. Thus, the line programming using VBI_DATA_Px_Ny registers identifies whether the data in line is teletext; the actual standard is identified by the VDP_TTXT_TYPE_MAN bit. To program the VDP_TTXT_TYPE_MAN bit, the VDP_TTXT_TYPE_MAN_ENABLE bit must be set to 1.
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VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map
0 (default)--Manual programming of the teletext type is disabled. 1--Manual programming of the teletext type is enabled. The user may select the data identification word (DID) and the secondary data identification word (SDID) through programming the ADF_DID[4:0] and ADF_SDID[5:0] bits, respectively, as explained in the following sections.
VDP_TTXT_TYPE_MAN[1:0], Specify the Teletext Type, Address 0x60 [1:0], User Sub Map
These bits specify the teletext type to be decoded. These bits are functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1.
Table 68. VDP_TTXT_TYPE_MAN Function
VDP_TTXT_ TYPE_MAN[1:0] 00 (default) 01 10 625/50 (PAL) Teletext-ITU-BT.653625/50-A Teletext-ITU-BT.653625/50-B (WST) Teletext-ITU-BT.653625/50-C Teletext-ITU-BT.653625/50-D 525/60 (NTSC) Reserved Teletext-ITU-BT.653525/60-B Teletext-ITU-BT.653525/60-C or EIA516 (NABTS) Teletext-ITU-BT.653525/60-D
ADF_DID[4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map
This bit selects the data ID word to be inserted into the ancillary data stream with the data decoded by the VDP. The default value of ADF_DID[4:0] is 10101.
ADF_SDID[5:0], User-Specified Secondary Data ID Word in Ancillary Data, Address 0x63 [5:0], User Sub Map
These bits select the secondary data ID word to be inserted in the ancillary data stream with the data decoded by the VDP. The default value of ADF_SDID[5:0] is 101010.
DUPLICATE_ADF, Enable Duplication/Spreading of Ancillary Data over Y and C Buses, Address 0x63 [7], User Sub Map
This bit determines whether the ancillary data is duplicated over both Y and C buses or if the data packets are spread between the two channels. 0 (default)--The ancillary data packet is spread across the Y and C data streams. 1--The ancillary data packet is duplicated on the Y and C data streams.
11
VDP Ancillary Data Output
Reading the data back via I2C may not be feasible for VBI data standards with high data rates (for example, teletext). An alternative is to place the sliced data in a packet in the line blanking of the digital output CCIR656 stream. This is available for all standards sliced by the VDP module. When data has been sliced on a given line, the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output (that is, data sliced from multiple lines are not buffered up and then emitted in a burst). Note that, due to the vertical delay through the comb filters, the line number on which the packet is placed differs from the line number on which the data was sliced. The user can enable or disable the insertion of VDP decoded results into the 656 ancillary streams by using the ADF_ENABLE bit.
ADF_MODE[1:0], Determine the Ancillary Data Output Mode, Address 0x62 [6:5], User Sub Map
These bits determine if the ancillary data output mode is in byte mode or nibble mode.
Table 69.
ADF_MODE[1:0] 00 (default) 01 10 Description Nibble mode Byte mode, no code restrictions Byte mode, but 0x00 and 0xFF prevented (0x00 replaced by 0x01, 0xFF replaced by 0xFE) Reserved
ADF_ENABLE, Enable Ancillary Data Output Through 656 Stream, Address 0x62 [7], User Sub Map
0 (default)--Disables insertion of VBI decoded data into ancillary 656 stream. 1--Enables insertion of VBI decoded data into ancillary 656 stream.
11
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The ancillary data packet sequence is explained in Table 70 and Table 71. The nibble output mode is the default mode of output from the ancillary stream when ancillary stream output is enabled. This format is in compliance with ITU-R BT.1364. These abbreviations are used in Table 70 and Table 71: *
EP--Even parity for Bit B8 to Bit B2. This means that the parity bit's EP is set so that an even number of 1s are in Bit B8 to Bit B2, including the parity bit, D8. CS--Checksum word. The CS word is used to increase confidence of the integrity of the ancillary data packet from the DID, SDID, and DC through user data-words (UDWs). It consists of 10 bits: a 9-bit calculated value and B9 as the inverse of B8. The checksum value B8 to B0 is equal to the nine LSBs of the sum of the nine LSBs of the DID, SDID, and DC and all UDWs in the packet. Prior to the start of the checksum count cycle, all checksum and carry bits are preset to 0. Any carry resulting from the checksum count cycle is ignored.
* *
*
*
EP--The MSB, B9, is the inverse of EP. This ensures that restricted Codes 0x00 and 0xFF do not occur. Line_number[9:0]--The line number of the line that immediately precedes the ancillary data packet. The line number is from the numbering system in ITU-R BT.470. The line number runs from 1 to 625 in a 625-line system and from 1 to 263 in a 525-line system. Note that, due to the vertical delay through the comb filters, the line number on which the packet is output differs from the line number on which the VBI data was sliced. Data Count--The data count specifies the number of UDWs in the ancillary stream for the standard. The total number of user data-words is four times the data count. Padding words may be introduced to make the total number of UDWs divisible by 4.
Table 70. Ancillary Data in Nibble Output Format
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . n-3 n-2 n-1 B9 0 1 1 EP EP EP EP EP EP EP EP EP EP EP EP . . . 1 1 B8 B8 0 1 1 EP EP EP EP EP EP EP EP EP EP EP EP . . . 0 0 0 Even_Field 0 0 0 0 0 0 . . . 0 0 0 0 0 0 0 0 . . . 0 0 . . . 0 0 Checksum . . . 0 0 0 0 padding[1:0] B7 0 1 1 0 B6 0 1 1 B5 0 1 1 B4 0 1 1 B3 0 1 1 B2 0 1 1 B1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 B0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 Description Ancillary data preamble. DID (data identification word). SDID (secondary data identification word). Data count. ID0 (User Data-Word 1). ID1 (User Data-Word 2). ID2 (User Data-Word 3). ID3 (User Data-Word 4). ID4 (User Data-Word 5). ID5 (User Data-Word 6). ID6 (User Data-Word 7). ID7 (User Data-Word 8). ID8 (User Data-Word 9). Pad 0x200. These padding words may be present depending on ancillary data type. User data-word xx. CS (checksum word).
I2C_DID6_2[4:0] I2C_SDID7_2[5:0] DC[4:0] VBI_DATA_STD[3:0] Line_number[9:5] Line_number[4:0] 0 VDP_TTXT_TYPE[1:0] VBI_WORD_1[7:4] VBI_WORD_1[3:0] VBI_WORD_2[7:4] VBI_WORD_2[3:0] VBI_WORD_3[7:4] . . . 0 0
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Table 71. Ancillary Data in Byte Output Format 1
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . n-3 n-2 n-1
1
B9 0 1 1 EP EP EP EP EP EP EP
B8 0 1 1 EP EP EP EP EP EP EP
B7 0 1 1 0 0 padding[1:0] 0 Even_Field 0
B6 0 1 1
B5 0 1 1
2
B4 B3 0 0 1 1 1 1 I2C_DID6_2[4:0] DC[4:0] VBI_DATA_STD[3:0] Line_number[9:5] Line_number[4:0]
B2 0 1 1
B1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0
B0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0
Description Ancillary data preamble. DID. SDID. Data count. ID0 (User Data-Word 1). ID1 (User Data-Word 2). ID2 (User Data-Word 3). ID3 (User Data-Word 4). ID4 (User Data-Word 5). ID5 (User Data-Word 6). ID6 (User Data-Word 7). ID7 (User Data-Word 8). ID8 (User Data-Word 9). Pad 0x200. These padding words may be present depending on ancillary data type. User data-word xx. CS (checksum word).
I C_SDID7_2[5:0]
. . . 1 1 B8
. . . 0 0
. . . 0 0
0 0 0 VBI_WORD_1[7:0] VBI_WORD_2[7:0] VBI_WORD_3[7:0] VBI_WORD_4[7:0] VBI_WORD_5[7:0] . . . . . . . . . 0 0 0 0 0 0 Checksum
VDP_TTXT_TYPE[1:0]
. . . 0 0
. . . 0 0
This mode does not fully comply with ITU-R BT.1364.
Structure of VBI Words in Ancillary Data Stream
Each VBI data standard has been split into a clock-run-in (CRI), a framing code (FC), and a number of data bytes (n). The data packet in the ancillary stream includes only the FC and data bytes. Table 72 shows the format of the VBI_WORD_x in the ancillary data stream.
Table 72. Structure of VBI Data-Words in Ancillary Stream
Ancillary Data Byte Number VBI_WORD_1 VBI_WORD_2 VBI_WORD_3 VBI_WORD_4 ... VBI_WORD_N + 3 Byte Type FC0 FC1 FC2 DB1 ... DBn Description Framing code [23:16] Framing code [15:8] Framing code [7:0] 1st data byte ... Last (nth) data byte
Table 73 shows the framing code and its valid length for VBI data standards supported by VDP.
Example
For teletext (B-WST), the framing code byte is 11100100 (0xE4), with bits shown in the order of transmission. For VBI_WORD_1 = 0x27, VBI_WORD_2 = 0x00, and VBI_WORD_3 = 0x00 translated into UDWs in the ancillary data stream for nibble mode is as follows: UDW5 [5:2] = 0010 UDW6 [5:2] = 0111 UDW7 [5:2] = 0000 (undefined bits set to 0) UDW8 [5:2] = 0000 (undefined bits set to 0) UDW9 [5:2] = 0000 (undefined bits set to 0) UDW10 [5:2] = 0000 (undefined bits set to 0) For byte mode: UDW5 [9:2] = 0010_0111 UDW6 [9:2] = 0000_0000 (undefined bits set to 0) UDW7 [9:2] = 0000_0000 (undefined bits set to 0)
VDP Framing Code
The length of the actual framing code depends on the VBI data standard. For uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. For standards with a smaller framing code length, the extra LSB bits are set to 0. The valid length of the framing code can be decoded from the VBI_DATA_STD bit available in ID0 (UDW 1). The framing code is always reported in the inversetransmission order.
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Data Bytes
The VBI_WORD_4 to VBI_WORD_N + 3 contains the datawords that were decoded by the VDP in the transmission order. The position of bits in bytes is in the inverse transmission order. For example, closed captioning has two user data bytes, as shown in Table 78. The data bytes in the ancillary data stream are as follows: VBI_WORD_4 = Byte 1 [7:0] VBI_WORD_5 = Byte 2 [7:0] The number of VBI_WORDS for each VBI data standard and the total number of UDWs in the ancillary data stream is shown in Table 74.
Table 73. Framing Code Sequence for Different VBI Standards
VBI Standard TTXT_SYSTEM_A (PAL) TTXT_SYSTEM_B (PAL) TTXT_SYSTEM_B (NTSC) TTXT_SYSTEM_C (PAL and NTSC) TTXT_SYSTEM_D (PAL and NTSC) VPS (PAL) VITC (NTSC and PAL) WSS (PAL) GEMSTAR_1x (NTSC) GEMSTAR_2x (NTSC) CCAP (NTSC and PAL) CGMS (NTSC) Length in Bits 8 8 8 8 8 16 1 24 3 11 3 1 Error-Free Framing Code Bits (In Order of Transmission) 11100111 11100100 11100100 11100111 11100101 10001010100011001 0 000111100011110000011111 001 1001_1011_101 001 0 Error-Free Framing Code Reported by VDP (In Reverse Order of Transmission) 11100111 00100111 00100111 11100111 10100111 1001100101010001 0 111110000011110001111000 100 101_1101_1001 100 0
Table 74. Total User Data-Words for Different VBI Standards 1
VBI Standard TTXT_SYSTEM_A (PAL) TTXT_SYSTEM_B (PAL) TTXT_SYSTEM_B (NTSC) TTXT_SYSTEM_C (PAL and NTSC) TTXT_SYSTEM_D (PAL and NTSC) VPS (PAL) VITC (NTSC and PAL) WSS (PAL) GEMSTAR_1x (NTSC) GEMSTAR_2x (NTSC) CCAP (NTSC and PAL) CGMS (NTSC) ADF Mode 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) 00 (nibble mode) 01,10 (byte mode) Framing Code UDWs 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 VBI Data-Words 74 37 84 42 68 34 66 33 68 34 26 13 18 9 4 2 4 2 8 4 4 2 6 3+3 No. of Padding Words 0 0 2 3 2 3 0 2 2 3 0 0 0 0 2 3 2 3 2 1 2 3 0 2 Total UDWs 84 44 96 52 80 44 76 42 80 44 36 20 28 16 16 12 16 12 20 12 16 12 16 12
1
The first four UDWs are always the ID.
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I2C Interface
Dedicated I2C readback registers are available for CCAP, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a high data rate standard, data extraction is supported only through the ancillary data packet. The details of these registers and their access procedure are described next.
User Interface for I2C Readback Registers
to be notified only when there is a change in the information content or loss of the information content. The user needs to enable content-based updating for the required standard through the GS_VPS_PDC_UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE bit shows the availability of that standard only when its content has changed. Content-based updating also applies to lines with lost data. Therefore, for standards like VPS, Gemstar, CGMS, and WSS, if no data arrives in the next four lines programmed, the corresponding AVAILABLE bit in the VDP_STATUS register is set high and the content in the I2C registers for that standard is set to 0. The user has to write high to the corresponding CLEAR bit so that when a valid line is decoded after some time, the decoded results are available in the I2C registers, with the AVAILABLE status bit set high. If content-based updating is enabled, the AVAILABLE bit is set high (assuming the CLEAR bit was written) in the following cases: * * * The data contents have changed. Data was being decoded and four lines with no data have been detected. No data was being decoded and new data is now being decoded.
The VDP decodes all enabled VBI data standards in real time. Because the I2C access speed is much lower than the decoded rate, when the registers are accessed, they may be updated with data from the next line. To avoid this, VDP has a self-clearing CLEAR bit and an AVAILABLE status bit accompanying all I2C readback registers. The user has to clear the I2C readback register by writing a high to the CLEAR bit. This resets the state of the AVAILABLE bit to low and indicates that the data in the associated readback registers is not valid. After the VDP decodes the next line of the corresponding VBI data, the decoded data is placed into the I2C readback register and the AVAILABLE bit is set to high to indicate that valid data is now available. Though the VDP decodes this VBI data in subsequent lines if present, the decoded data is not updated to the readback registers until the CLEAR bit is set high again. However, this data is available through the 656 ancillary data packets. The CLEAR and AVAILABLE bits are in the VDP_CLEAR (0x78, User Sub Map, write only) and VDP_STATUS (0x78, User Sub Map, read only) registers.
Example I C Readback Procedure The following tasks have to be performed to read one packet (line) of PDC data from the decoder:
2
GS_VPS_PDC_UTC_CB_CHANGE, Enable ContentBased Updating for Gemstar/VPS/PDC/UTC, Address 0x9C [5], User Sub Map
0--Disables content-based updating. 1 (default)--Enables content-based updating.
1.
Write 10 to I2C_GS_VPS_PDC_UTC[1:0] (0x9C, User Sub Map) to specify that PDC data has to be updated to I2C registers. Write high to the GS_PDC_VPS_UTC_CLEAR bit (0x78, User Sub Map) to enable I2C register updating. Poll the GS_PDC_VPS_UTC_AVL bit (0x78, User Sub Map) going high to check the availability of the PDC packets. Read the data bytes from the PDC I2C registers. Repeat Step 1 to Step 3 to read another line or packet of data.
WSS_CGMS_CB_CHANGE, Enable Content-Based Updating for WSS/CGMS, Address 0x9C [4], User Sub Map
0--Disables content-based updating. 1 (default)--Enables content-based updating.
2. 3.
VDP--Interrupt-Based Reading of VDP I2C Registers
Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit. The user can configure the video decoder to trigger an interrupt request on the INTRQ pin in response to the valid data available in I2C registers. This function is available for the following data types: *
CGMS or WSS: The user can select either triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. Selection is made via the WSS_CGMS_CB_CHANGE bit.
4.
To read a packet of CCAP, CGMS, or WSS data, only Step 1 to Step 3 are required because they have dedicated registers.
VDP--Content-Based Data Update
For certain standards like WSS, CGMS, Gemstar, PDC, UTC, and VPS, the information content in the signal transmitted remains the same over numerous lines, and the user may want
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*
Gemstar, PDC, VPS, or UTC: The user can select to trigger an interrupt request each time sliced data is available or to trigger an interrupt request only when the sliced data has changed. Selection is made via the GS_VPS_PDC_UTC_CB_ CHANGE bit.
2
VDP_VITC_MSKB, Address 0x50 [6], User Sub Map
0 (default)--Disables interrupt on VDP_VITC_Q signal. 1--Enables interrupt on VDP_VITC_Q signal.
Interrupt Status Register Details
The following read-only bits contain data detection information from the VDP module since the status bit was last cleared or unmasked.
The sequence for the interrupt-based reading of the VDP I C data registers is as follows for the CCAP standard: 1. User unmasks CCAP interrupt mask bit (0x50 Bit 0, User Sub Map = 1). CCAP data occurs on the incoming video. VDP slices CCAP data and places it into the VDP readback registers. The VDP CCAP AVAILABLE bit goes high, and the VDP module signals to the interrupt controller to stimulate an interrupt request (for CCAP in this case). The user reads the interrupt status bits (User Sub Map) and sees that new CCAP data is available (0x4E Bit 0, User Sub Map = 1). The user writes 1 to the CCAP interrupt clear bit (0x4F Bit 0, User Sub Map = 1) in the interrupt I2C space (this is a self-clearing bit). This clears the interrupt on the INTRQ pin but does not have an effect in the VDP I2C area. The user reads the CCAP data from the VDP I2C area. The user writes to Bit CC_CLEAR in the VDP_STATUS[0] register, (0x78 Bit 0, User Sub Map = 1) to signify the CCAP data has been read (therefore the VDP CCAP can be updated at the next occurrence of CCAP). Back to Step 2.
VDP_CCAPD_Q, Address 0x4E [0], User Sub Map
0 (default)--CCAP data has not been detected. 1--CCAP data has been detected.
2.
VDP_CGMS_WSS_CHNGD_Q, Address 0x4E [2], User Sub Map
0 (default)--CGMS or WSS data has not been detected. 1--CGM or WSS data has been detected.
3.
4.
VDP_GS_VPS_PDC_UTC_CHNG_Q, Address 0x4E [4], User Sub Map
0 (default)--Gemstar, PDC, UTC, or VPS data has not been detected. 1--Gemstar, PDC, UTC, or VPS data has been detected.
5. 6.
VDP_VITC_Q, Address 0x4E [6], User Sub Map, Read Only
0 (default)--VITC data has not been detected. 1--VITC data has been detected.
7.
Interrupt Mask Register Details
The following bits set the interrupt mask on the signal from the VDP VBI data slicer.
Interrupt Status Clear Register Details
It is not necessary to write 0 to these write-only bits because they automatically reset after they have been set to 1 (selfclearing).
VDP_CCAPD_MSKB, Address 0x50 [0], User Sub Map
0 (default)--Disables interrupt on VDP_CCAPD_Q signal. 1--Enables interrupt on VDP_CCAPD_Q signal.
VDP_CCAPD_CLR, Address 0x4F [0], User Sub Map
1--Clears VDP_CCAP_Q bit.
VDP_CGMS_WSS_CHNGD_MSKB, Address 0x50 [2], User Sub Map
0 (default)--Disables interrupt on VDP_CGMS_WSS_ CHNGD_Q signal. 1--Enables interrupt on VDP_CGMS_WSS_CHNGD_Q signal.
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2], User Sub Map
1--Clears VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR, Address 0x4F [4], User Sub Map
1--Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_MSKB, Address 0x50 [4], User Sub Map
0 (default)--Disables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q signal. 1--Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q signal.
VDP_VITC_CLR, Address 0x4F [6], User Sub Map
1--Clears VDP_VITC_Q bit.
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I2C READBACK REGISTERS
Teletext
Because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. However, a TTXT_AVL bit has been provided in I2C so that the user can check whether the VDP has detected teletext or not. Note that the TTXT_AVL bit is a plain status bit and does not use the protocol identified in the I2C Interface section.
WST_PKT_DECODE_DISABLE, Disable Hamming Decoding of Bytes in WST, Address 0x60 [3], User Sub Map
0--Enables hamming decoding of WST packets. 1 (default)--Disables hamming decoding of WST packets. For hamming-coded bytes, the dehammed nibbles are output along with some error information from the hamming decoder as follows: * * Input hamming coded byte: {D3, P3, D2, P2, D1, P1, D0, P0} (bits in decoded order) Output dehammed byte: {E1, E0, 0, 0, D3', D2', D1', D0'} (Di' - corrected bits, Ei error information).
TTXT_AVL, Teletext Detected Status, Address 0x78 [7], User Sub Map, Read Only
0--Teletext was not detected. 1--Teletext was detected.
WST Packet Decoding
For WST only, the VDP decodes the magazine and row address of teletext packets and further decodes the packet's 8 x 4 hamming coded words. This feature can be disabled using the WST_PKT_ DECODE_ DISABLE bit (Bit 3, Register 0x60, User Sub Map). This feature is valid for WST only.
Table 75. Error Bits in the Dehammed Output Byte
E[1:0] 00 01 10 11 Error Information No errors detected Error in P4 Double error Single error found and corrected Output Data Bits in Nibble Okay Okay Bad Okay
Table 76 describes the WST packets that are decoded.
Table 76. WST Packet Description
Packet Header Packet (X/00) Byte 1st 2nd 3rd 4th 5th to 10th 11th to 42nd 1st 2nd 3rd to 42nd 1st 2nd 3rd 4th to 10th 11th to 23rd 24th to 42nd 1st 2nd 3rd 4th to 10th 11th to 23rd 24th to 42nd 1st 2nd 3rd 4th to 42nd Description Magazine number--Dehammed Byte 4 Row number--Dehammed Byte 5 Page number--Dehammed Byte 6 Page number--Dehammed Byte 7 Control Bytes--Dehammed Byte 8 to Byte 13 Raw data bytes Magazine number--Dehammed Byte 4 Row number--Dehammed Byte 5 Raw data bytes Magazine number--Dehammed Byte 4 Row number--Dehammed Byte 5 Design Code--Dehammed Byte 6 Dehammed initial teletext page, Byte 7 to Byte 12 UTC bytes--Dehammed Bytes 13 to Byte 25 Raw status bytes Magazine number--Dehammed Byte 4 Row number--Dehammed Byte 5 Design Code--Dehammed Byte 6 Dehammed initial teletext page, Byte 7 to Byte 12 PDC bytes--Dehammed Byte 13 to Byte 25 Raw status bytes Magazine number--Dehammed Byte 4 Row number--Dehammed Byte 5 Design Code--Dehammed Byte 6 Raw data bytes
Text Packets (X/01 to X/25) 8/30 (Format 1) Packet Design Code = 0000 or 0001 UTC
8/30 (Format 2) Packet Design Code = 0010 or 0011 PDC
X/26, X/27, X/28, X/29, X/30, X/31 1
1
For X/26, X/28, and X/29 further decoding needs 24 x 18 hamming decoding. Not supported at present.
Rev. A | Page 59 of 112
ADV7180
CGMS and WSS
The CGMS and WSS data packets convey the same type of information for different video standards. WSS is for PAL and CGMS is for NTSC, so the CGMS and WSS readback registers are shared. WSS is biphase coded; the VDP does a biphase decoding to produce the 14 raw WSS bits in the CGMS/WSS readback I2C registers and to set the CGMS_WSS_AVL bit.
CGMS_WSS_AVL, CGMS/WSS Available, Address 0x78 [2], User Sub Map, Read Only
0--CGMS/WSS was not detected. 1--CGMS/WSS was detected.
CGMS_WSS_DATA_0[3:0], Address 0x7D [3:0]; CGMS_WSS_DATA_1[7:0], Address 0x7E [7:0]; CGMS_WSS_DATA_2[7:0], Address 0x7F [7:0]; User Sub Map, Read Only
These bits hold the decoded CGMS or WSS data. Refer to Figure 43 and Figure 44 for the I2C to WSS and CGMS bit mapping.
VDP_CGMS_WSS_ DATA_1[5:0] 0 1 2 3 4 5 ACTIVE VIDEO
CGMS_WSS_CLEAR, CGMS/WSS Clear, Address 0x78 [2], User Sub Map, Write Only, Self-Clearing
1--Reinitializes the CGMS/WSS readback registers.
VDP_CGMS_WSS_DATA_2 0
RUN-IN SEQUENCE
1
2
3
4
5
6
7
START CODE
11.0s 42.5s
05700-039
38.4s
Figure 43. WSS Waveform
+100 IRE REF +70 IRE 0 VDP_CGMS_WSS_DATA_2 1 2 3 4 5 6 7 0 VDP_CGMS_WSS_DATA_1 1 2 3 4 5 6 7
VDP_CGMS_WSS_ DATA_0[3:0] 0 1 2 3
0 IRE 49.1s 0.5s CRC SEQUENCE
05700-040
-40 IRE
11.2s 2.235s 20ns
Figure 44. CGMS Waveform
Table 77. CGMS Readback Registers 1
Signal Name CGMS_WSS_DATA_0[3:0] CGMS_WSS_DATA_1[7:0] CGMS_WSS_DATA_2[7:0]
1
Register Location VDP_CGMS_WSS_DATA_0[3:0] VDP_CGMS_WSS_DATA_1[7:0] VDP_CGMS_WSS_DATA_2[7:0]
125 126 127
Address (User Sub Map) 0x7D 0x7E 0x7F
The register is a readback register; default value does not apply.
Rev. A | Page 60 of 112
ADV7180
CCAP
Two bytes of decoded closed caption data are available in the I2C registers. The field information of the decoded CCAP data can be obtained from the CC_EVEN_FIELD bit (Register 0x78).
CC_EVEN_FIELD, Address 0x78 [1], User Sub Map, Read Only
Identifies the field from which the CCAP data was decoded. 0--Closed captioning was detected on an odd field. 1--Closed captioning was detected on an even field.
CC_CLEAR, Closed Caption Clear, Address 0x78 [0], User Sub Map, Write Only, Self-Clearing
1--Reinitializes the CCAP readback registers.
VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map, Read Only
Decoded Byte 1 of CCAP data.
CC_AVL, Closed Caption Available, Address 0x78 [0], User Sub Map, Read Only
0--Closed captioning was not detected. 1--Closed captioning was detected.
VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map, Read Only
Decoded Byte 2 of CCAP data.
10.5 0.25s
12.91s
7 CYCLES OF 0.5035MHz (CLOCK RUN-IN)
50 IRE
S T A R T
0123456 701234567 P A R I T Y P A R I T Y
40 IRE
27.382s
33.764s
Figure 45. CCAP Waveform and Decoded Data Correlation
Table 78. CCAP Readback Registers 1
Signal Name CCAP_BYTE_1[7:0] CCAP_BYTE_2[7:0]
1
Register Location VDP_CCAP_DATA_0[7:0] VDP_CCAP_DATA_1[7:0]
121 122
Address (User Sub Map) 0x79 0x7A
The register is a readback register; default value does not apply.
Rev. A | Page 61 of 112
05700-041
REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s
VDP_CCAP_D ATA_0
VDP_CCAP_D ATA_1
ADV7180
VITC
VITC has a sequence of 10 syncs in between each data byte. The VDP strips these syncs from the data stream to output only the data bytes. The VITC results are available in Register VDP_VITC_DATA_0 to Register VDP_VITC_DATA_8 (Register 0x92 to Register 0x9A, User Sub Map). The VITC has a CRC byte at the end; the syncs in between each data byte are also used in this CRC calculation. Because the syncs in between each data byte are not output, the CRC is calculated internally. The calculated CRC is available for the user in the VITC_CALC_CRC register (Resister 0x9B, User Sub Map). Once the VDP completes decoding the VITC line, the VITC_DATA and VITC_CALC_CRC registers are updated and the VITC_AVL bit is set.
VITC_CLEAR, VITC Clear, Address 0x78 [6], User Sub Map, Write Only, Self-Clearing
1--Reinitializes the VITC readback registers.
VITC_AVL, VITC Available, Address 0x78 [6], User Sub Map
0--VITC data was not detected. 1--VITC data was detected.
VITC Readback Registers
See Figure 46 for the I2C to VITC bit mapping.
BIT0, BIT1
BIT88, BIT89
VITC WAVEFORM
Figure 46. VITC Waveform and Decoded Data Correlation
Table 79. VITC Readback Registers 1
Signal Name VITC_DATA_0[7:0] VITC_DATA_1[7:0] VITC_DATA_2[7:0] VITC_DATA_3[7:0] VITC_DATA_4[7:0] VITC_DATA_5[7:0] VITC_DATA_6[7:0] VITC_DATA_7[7:0] VITC_DATA_8[7:0] VITC_CALC_CRC[7:0]
1
Register Location VDP_VITC_DATA_0[7:0] (VITC Bits [9:2]) VDP_VITC_DATA_1[7:0] (VITC Bits [19:12]) VDP_VITC_DATA_2[7:0] (VITC Bits [29:22]) VDP_VITC_DATA_3[7:0] (VITC Bits [39:32]) VDP_VITC_DATA_4[7:0] (VITC Bits [49:42]) VDP_VITC_DATA_5[7:0] (VITC Bits [59:52]) VDP_VITC_DATA_6[7:0] (VITC Bits [69:62]) VDP_VITC_DATA_7[7:0] (VITC Bits [79:72]) VDP_VITC_DATA_8[7:0] (VITC Bits [89:82]) VDP_VITC_CALC_CRC[7:0]
146 147 148 149 150 151 152 153 154 155
Address (User Sub Map) 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B
The register is a readback register; default value does not apply.
Rev. A | Page 62 of 112
05700-042
TO
ADV7180
VPS/PDC/UTC/GEMSTAR
The readback registers for VPS, PDC, and UTC are shared. Gemstar is a high data rate standard and is available only through the ancillary stream. However, for evaluation purposes, any one line of Gemstar is available through the I2C registers sharing the same register space as PDC, UTC, and VPS. Therefore, only VPS, PDC, UTC, or Gemstar can be read through the I2C at a time. To identify the data that should be made available in the I2C registers, the user must program I2C_GS_VPS_PDC_UTC[1:0] (Register Address 0x9C, User Sub Map).
I2C_GS_VPS_PDC_UTC [1:0] (VDP), Address 0x9C [6:5], User Sub Map
VDP supports autodetection of the Gemstar standard, either Gemstar 1x or Gemstar 2x, and decodes accordingly. For the autodetection mode to work, the user must set the AUTO_DETECT_GS_TYPE I2C bit (Register 0x61, User Sub Map) and program the decoder to decode Gemstar 2x on the required lines through line programming. The type of Gemstar decoded can be determined by observing the GS_DATA_TYPE bit (Register 0x78, User Sub Map).
AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
0 (default)--Disables autodetection of Gemstar type. 1--Enables autodetection of Gemstar type.
GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
Specifies which standard result is available for I2C readback.
GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
Identifies the decoded Gemstar data type. 0--Gemstar 1x mode is detected. Read 2 data bytes from 0x84. 1--Gemstar 2x mode is detected. Read 4 data bytes from 0x84. The Gemstar data that is available in the I2C register could be from any line of the input video on which Gemstar was decoded. To read the Gemstar data on a particular video line, the user should use the manual configuration described in Table 66 and Table 67 and enable Gemstar decoding only on the required line.
1--Reinitializes the GS/PDC/VPS/UTC data readback registers.
GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Address 0x78 [4], User Sub Map, Read Only
0--One of GS, PDC, VPS, or UTC data was not detected. 1--One of GS, PDC, VPS, or UTC data was detected.
VDP_GS_VPS_PDC_UTC, Readback Registers, Addresses 0x84 to 0x87 See Table 81.
PDC/UTC
PDC and UTC are data transmitted through Teletext Packet 8/30 Format 2 (Magazine 8, Row 30, Design Code 2 or 3), and Packet 8/30 Format 1 (Magazine 8, Row 30, Design Code 0 or 1). Thus, if PDC or UTC data is to be read through I2C, the corresponding teletext standard (WST or PAL System B) should be decoded by VDP. The whole teletext decoded packet is output on the ancillary data stream. The user can look for the magazine number, row number, and design code and qualify the data as PDC, UTC, or neither of these. If PDC/UTC packets have been identified, Byte 0 to Byte 12 are updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12 registers, and the GS_VPS_PDC_UTC_AVL bit is set. The full packet data is also available in the ancillary data format. Note that the data available in the I2C register depends on the status of the WST_PKT_DECODE_DISABLE bit (Bit 3, Subaddress 0x60, User Sub Map).
VPS
The VPS data bits are biphase decoded by the VDP. The decoded data is available in both the ancillary stream and in the I2C readback registers. VPS decoded data is available in the VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12 registers (Address 0x84 to Address 0x90, User Sub Map). The GS_VPS_ PDC_UTC_AVL bit is set if the user programmed I2C_GS_VPS_PDC_UTC to 01, as explained in Table 80.
GEMSTAR
The Gemstar-decoded data is made available in the ancillary stream, and any one line of Gemstar is also available in the I2C registers for evaluation purposes. To read Gemstar results through the I2C registers, the user must program I2C_GS_VPS_PDC_UTC to 00, as explained in Table 80.
Table 80. I2C_GS_VPS_PDC_UTC[1:0] Function
I2C_GS_VPS_PDC_UTC[1:0] 00 (default) 01 10 11 Description Gemstar 1x/2x VPS PDC UTC
Rev. A | Page 63 of 112
ADV7180
Table 81. GS/VPS/PDC/UTC Readback Registers 1
Signal Name GS_VPS_PDC_UTC_BYTE_0[7:0] GS_VPS_PDC_UTC_BYTE_1[7:0] GS_VPS_PDC_UTC_BYTE_2[7:0] GS_VPS_PDC_UTC_BYTE_3[7:0] VPS_PDC_UTC_BYTE_4[7:0] VPS_PDC_UTC_BYTE_5[7:0] VPS_PDC_UTC_BYTE_6[7:0] VPS_PDC_UTC_BYTE_7[7:0] VPS_PDC_UTC_BYTE_8[7:0] VPS_PDC_UTC_BYTE_9[7:0] VPS_PDC_UTC_BYTE_10[7:0] VPS_PDC_UTC_BYTE_11[7:0] VPS_PDC_UTC_BYTE_12[7:0]
1
Register Location VDP_GS_VPS_PDC_UTC_0[7:0] VDP_GS_VPS_PDC_UTC_1[7:0] VDP_GS_VPS_PDC_UTC_2[7:0] VDP_GS_VPS_PDC_UTC_3[7:0] VDP_VPS_PDC_UTC_4[7:0] VDP_VPS_PDC_UTC_5[7:0] VDP_VPS_PDC_UTC_6[7:0] VDP_VPS_PDC_UTC_7[7:0] VDP_VPS_PDC_UTC_8[7:0] VDP_VPS_PDC_UTC_9[7:0] VDP_VPS_PDC_UTC_10[7:0] VDP_VPS_PDC_UTC_11[7:0] VDP_VPS_PDC_UTC_12[7:0]
Dec Address (User Sub Map) 132d 133d 134d 135d 136d 137d 138d 139d 140d 141d 142d 143d 144d
Hex Address (User Sub Map) 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90
The default value does not apply to readback registers.
VBI System 2
The user has an option of using a different VBI data slicer called VBI System 2. This data slicer is used to decode Gemstar and closed caption VBI signals only. Using this system, the Gemstar data is only available in the ancillary data stream. A special mode enables one line of data to be read back through I2C. For details about using I2C readback with the VBI System 2 data slicer, contact local Analog Devices field applications engineers or local Analog Devices distributor.
GDE_SEL_OLD_ADF, Address 0x4C [3], User Sub Map
The ADV7180 has a new ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer. The new ancillary data formatter is used by setting GDE_SEL_OLD_ADF to 0 (default). If this bit is set low, refer to Table 70 and Table 71 for information about how the data is packaged in the ancillary data stream. To use the old ancillary data formatter (to be backward compatible with the ADV7183B), set GDE_SEL_OLD_ADF to 1. The ancillary data format in this section refers to the ADV7183B-compatible ancillary data formatter. 0 (default)--Enables new ancillary data system for use with VDP and VBI System 2. 1--Enables old ancillary data system for use with VBI System 2 only (ADV7183B compatible). The format of the data packet depends on the following criteria: * * * Transmission is 1x or 2x. Data is output in 8-bit or 4-bit format (see the description of the bit). Data is closed caption (CCAP) or Gemstar compatible.
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports 1x and 2x data transmissions. In addition, it can serve as a closed caption decoder. Gemstar-compatible data transmissions can occur only in NTSC. Closed caption data can be decoded in both PAL and NTSC. The block can be configured via I2C as follows: * * * GDECEL[15:0] allows data recovery on selected video lines on even fields to be enabled or disabled. GDECOL[15:0] enables the data recovery on selected lines for odd fields. GDECAD configures the way in which data is embedded in the video data stream.
2
The recovered data is not available through I C, but is inserted into the horizontal blanking period of an ITU-R BT.656-compatible data stream. The data format is intended to comply with the recommendation by the International Telecommunications Union, ITU-R BT.1364. For more information, visit the International Telecommunication Union website. See Figure 47.
Data packets are output if the corresponding enable bit is set (see the GDECEL[15:0] and GDECOL[15:0] descriptions) the decoder detects the presence of data. This means that for video lines where no data has been decoded, no data packet is output even if the corresponding line enable bit is set.
Rev. A | Page 64 of 112
ADV7180
Each data packet starts immediately after the EAV code of the preceding line. Figure 47 and Table 82 show the overall structure of the data packet. Entries within the packet are as follows: * * Fixed preamble sequence of 0x00, 0xFF, and 0xFF. Data identification word (DID). The value for the DID marking a Gemstar or CCAP data packet is 0x140 (10-bit value). Secondary data identification word (SDID), which contains information about the video line from which data was retrieved, whether the Gemstar transmission was of 1x or 2x format, and whether it was retrieved from an even or odd field.
DATA IDENTIFICATION
* * *
Data count byte, giving the number of user data-words that follow. User data section. Optional padding to ensure that the length of the user data-word section of a packet is a multiple of 4 bytes (requirement as set in ITU-R BT.1364). Checksum byte.
*
*
Table 82 lists the values within a generic data packet that is output by the ADV7180 in 8-bit format.
SECONDARY DATA IDENTIFICATION DATA COUNT OPTIONAL PADDING BYTES CHECK SUM
05700-043
00
FF
FF
DID
SDID
USER DATA
PREAMBLE FOR ANCILLARY DATA
USER DATA (4 OR 8 WORDS)
Figure 47. Gemstar and CCAP Embedded Data Packet (Generic)
Table 82. Generic Data Output Packet
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 EP EP EP EP EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 2X 0 0 0 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] DC[1] D[2] 0 1 1 0 DC[0] D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[2] 0 D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count (DC) User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum
word1[7:4] word1[3:0] word2[7:4] word2[3:0] word3[7:4] word3[3:0] word4[7:4] word4[3:0] CS[4] CS[3]
Table 83. Data Byte Allocation
2x 1 1 0 0 Raw Information Bytes Retrieved from the Video Line 4 4 2 2 GDECAD 0 1 0 1 User Data-Words (Including Padding) 8 4 4 4 Padding Bytes 0 0 0 2 DC[1:0] 10 01 01 01
Rev. A | Page 65 of 112
ADV7180
Gemstar Bit Names
* DID--The data identification value is 0x140 (10-bit value). Care has been taken so that in 8-bit systems, the two LSBs do not carry vital information. EP and EP--The EP bit is set to ensure even parity on data-word D[8:0]. Even parity means there is always an even number of 1s within the D[8:0] bit arrangement. This includes the EP bit. EP describes the logic inverse of EP and is output on D[9]. The EP is output to ensure that the reserved codes of 00 and FF do not occur. EF--Even field identifier. EF = 1 indicates that the data was recovered from a video line on an even field. 2x--This bit indicates whether the data sliced was in Gemstar 1x or 2x format. A high indicates 2x format. The 2x bit determines whether the raw information retrieved from the video line was two bytes or four bytes. The state of the GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). Padding bytes are then added where necessary. line[3:0]--This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved. Refer to Table 92 and Table 93. * * DC[1:0]--Data count value. The number of UDWs in the packet divided by 4. The number of UDWs in any packet must be an integral number of 4. Padding may be required at the end, as set in ITU-R BT.1364. See Table 83. CS[8:2]--The checksum is provided to determine the integrity of the ancillary data packet. It is calculated by summing up D[8:2] of DID, SDID, the data count byte, and all UDWs, and ignoring any overflow during the summation. Because all data bytes that are used to calculate the checksum have their 2 LSBs set to 0, the CS[1:0] bits are also always 0.
*
* *
CS[8]--describes the logic inversion of CS[8]. The value CS[8] is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xFF do not occur. Table 84 to Table 89 outline the possible data packages.
Gemstar_2x Format, Half-Byte Output Mode
Half-byte output mode is selected by setting CDECAD to 0; full-byte output mode is selected by setting CDECAD to 1. See the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section.
*
Gemstar_1x Format
Half-byte output mode is selected by setting CDECAD to 0, full-byte output mode is selected by setting CDECAD to 1. See the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section.
Table 84. Gemstar_2x Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 EP EP EP EP EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 1 D[2] 0 1 1 0 0 D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum
Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] Gemstar word3[7:4] Gemstar word3[3:0] Gemstar word4[7:4] Gemstar word4[3:0] CS[4] CS[3] CS[2]
Rev. A | Page 66 of 112
ADV7180
Table 85. Gemstar_2x Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 1 0 D[5] 0 1 1 0 0 D[4] D[3] 0 0 1 1 1 1 0 0 line[3:0] 0 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CS[8]
CS[8]
CS[7]
Gemstar word1[7:0] Gemstar word2[7:0] Gemstar word3[7:0] Gemstar word4[7:0] CS[6] CS[5] CS[4]
CS[3]
CS[2]
Table 86. Gemstar_1x Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] CS[4] CS[3] CS[2]
Table 87. Gemstar_1x Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 CS[8]
0 0 CS[8]
0 0 CS[7]
Gemstar word1[7:0] Gemstar word2[7:0] 0 0 0 0 0 0 CS[6] CS[5] CS[4]
0 0 CS[3]
0 0 CS[2]
Rev. A | Page 67 of 112
ADV7180
Table 88. NTSC CCAP Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[2] CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3]
Table 89. NTSC CCAP Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 CS[8]
0 0 CS[8]
0 0 CS[7]
CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5]
0 0 CS[4]
0 0 CS[3]
0 0 CS[2]
Rev. A | Page 68 of 112
ADV7180
Table 90. PAL CCAP Data, Half-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[2] CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum
CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3]
Table 91. PAL CCAP Data, Full-Byte Mode
Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum
1 1 CS[8]
0 0 CS[8]
0 0 CS[7]
CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5]
0 0 CS[4]
0 0 CS[3]
0 0 CS[2]
NTSC CCAP Data
Half-byte output mode is selected by setting CDECAD to 0, and the full-byte mode is enabled by setting CDECAD to 1. See the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. The data packet formats are shown in Table 88 and Table 89. Only closed caption data can be embedded in the output data stream. NTSC closed caption data is sliced on Line 21d of even and odd fields. The corresponding enable bit has to be set high. See the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section and the GDECOL[15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] section.
See the GDECEL[15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0] section and the GDECOL[15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] section.
GDECEL[15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]
The 16 bits of GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting the bit enables the decoder block trying to find Gemstar or closed caption-compatible data on that particular line. Setting the bit to 0 prevents the decoder from trying to retrieve data. See Table 92 and Table 93. To retrieve closed caption data services on NTSC (Line 284), GDECEL[11] must be set. To retrieve closed caption data services on PAL (Line 335), GDECEL[14] must be set. The default value of GDECEL[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field. The user should only enable Gemstar slicing on lines where VBI data is expected.
PAL CCAP Data
Half-byte output mode is selected by setting CDECAD to 0, and full-byte output mode is selected by setting CDECAD to 1. See the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Table 90 and Table 91 list the bytes of the data packet. Only closed caption data can be embedded in the output data stream. PAL closed caption data is sliced from Line 22 and Line 335. The corresponding enable bits must be set.
Rev. A | Page 69 of 112
ADV7180
Table 92. NTSC Line Enable Bits and Corresponding Line Numbering
line[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Line Number (ITU-R BT.470) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 273 (10) 274 (11) 275 (12) 276 (13) 277 (14) 278 (15) 279 (16) 280 (17) 281 (18) 282 (19) 283 (20) 284 (21) 285 (22) 286 (23) 287 (24) 288 (25) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar
GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0]
The decoded data from Gemstar-compatible transmissions or closed caption-compatible transmission is inserted into the horizontal blanking period of the respective line of video. A potential problem can arise if the retrieved data bytes have a value of 0x00 or 0xFF. In an ITU-R BT.656-compatible data stream, these values are reserved and used only to form a fixed preamble. The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways: * Insert all data straight into the data stream, even the reserved values of 0x00 and 0xFF, if they occur. This may violate output data format specification ITU-R BT.1364. Split all data into nibbles and insert the half-bytes over double the number of cycles in a 4-bit format.
*
0 (default)--The data is split into half-bytes and inserted. 1--The data is output straight into the data stream in 8-bit format.
Table 93. PAL Line Enable Bits and Line Numbering
line[3:0] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 Line Number (ITU-R BT.470) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 321 (8) 322 (9) 323 (10) 324 (11) 325 (12) 326 (13) 327 (14) 328 (15) 329 (16) 330 (17) 331 (18) 332 (19) 333 (20) 334 (21) 335 (22) 336 (23) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid
GDECOL[15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]
The 16 bits of GDECOL[15:0] form a collection of 16 individual line decode enable signals. See Table 92 and Table 93. To retrieve closed caption data services on NTSC (Line 21), GDECOL[11] must be set. To retrieve closed caption data services on PAL (Line 22), GDECOL[14] must be set. The default value of GDECOL[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field. The user should only enable Gemstar slicing on lines where VBI data is expected.
Rev. A | Page 70 of 112
ADV7180
Letterbox Detection
Incoming video signals may conform to different aspect ratios (16:9 wide screen or 4:3 standard). For certain transmissions in the wide-screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits that WSS contains. In the absence of a WSS sequence, letterbox detection can be used to find wide-screen signals. The detection algorithm examines the active video content of lines at the start and end of a field. If black lines are detected, this may indicate that the currently shown picture is in wide-screen format. The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold, and a decision is made as to whether or not a particular line is black. The threshold value needed may depend on the type of input signal; some control is provided via LB_TH[4:0]. There is no letterbox detected bit. Read the LB_LCT[7:0] and LB_LCB[7:0] register values to determine whether or not the letterbox-type video is present in software.
LB_LCT[7:0], Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM[7:0], Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB[7:0], Letterbox Line Count Bottom, Address 0x9D [7:0]
Table 94. LB_LCx Access Information
Signal Name LB_LCT[7:0] LB_LCM[7:0] LB_LCB[7:0] Address 0x9B 0x9C 0x9D
LB_TH[4:0], Letterbox Threshold Control, Address 0xDC [4:0]
Table 95. LB_TH Function
LB_TH[4:0] 01100 (default) 01101 to 10000 00000 to 01011 Description Default threshold for detection of black lines. Increase threshold (need larger active video content before identifying nonblack lines). Decrease threshold (even small noise levels can cause the detection of nonblack lines).
Detection at the Start of a Field
The ADV7180 expects a section of at least six consecutive black lines of video at the top of a field. Once those lines are detected, Register LB_LCT[7:0] reports the number of black lines that were actually found. By default, the ADV7180 starts looking for those black lines in sync with the beginning of active video, for example, immediately after the last VBI video line. LB_SL[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. The detection window closes in the middle of the field.
LB_SL[3:0], Letterbox Start Line, Address 0xDD [7:4]
The LB_SL[3:0] bits are set at 0100 by default. For an NTSC signal, this window is from Line 23 to Line 286. By changing the bits to 0101, the detection window starts on Line 24 and ends on Line 287.
Detection at the End of a Field
The ADV7180 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the LB_LCB[7:0] value. The activity window for letterbox detection (end of field) starts in the middle of an active field. Its end is programmable via LB_EL[3:0].
LB_EL[3:0], Letterbox End Line, Address 0xDD [3:0]
The LB_EL[3:0] bits are set at 1101 by default. This means that the letterbox detection window ends with the last active video line. For an NTSC signal, this window is from Line 262 to Line 525. By changing the bits to 1100, the detection window starts on Line 261 and ends on Line 254.
Detection at the Midrange
Some transmissions of wide-screen video include subtitles within the lower black box. If the ADV7180 finds at least two black lines followed by some more nonblack video, for example, the subtitle followed by the remainder of the bottom black block, it reports a midcount via LB_LCM[7:0]. If no subtitles are found, LB_LCM[7:0] reports the same number as LB_LCB[7:0]. There is a 2-field delay in reporting any line count parameter.
Rev. A | Page 71 of 112
ADV7180 PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 96, Table 97, and Table 98 summarize the various functions that the ADV7180 pins can have in different modes of operation. The ordering of components, for example, Cr vs. Cb for Channels A, B, and C can be changed. Refer to the SWPC, Swap Pixel Cr/Cb, Address 0x27 [7] section. Table 96 indicates the default positions for the Cr/Cb components.
SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped. When SWPC is 0 (default), no swapping is allowed. When SWPC is 1, the Cr and Cb values can be swapped.
LLC_PAD_SEL[2:0], LLC1 Output Selection, Address 0x8F [6:4]
The following I2C write allows the user to select between LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz). The LLC2 signal is useful for LLC2-compatible wide bus (16-bit) output modes. See the OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2] section for additional information. The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments to the clock edges, can be altered by using the polarity LLC pin. When LLC_PAD_SEL is 000, the output is nominally 27 MHz LLC on the LLC1 pin (default). When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz LLC on the LLC2 pin.
OF_SEL[3:0], Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7180 pixel port can be configured are under the control of OF_SEL[3:0]. See Table 98 for details. The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the section LLC_PAD_SEL[2:0], LLC1 Output Selection, Address 0x8F [6:4].
Table 96. ADV7180 LQFP-64 P15 to P0 Output/Input Pin Mapping
Format and Mode Video Out, 8-Bit, 4:2:2 Video Out, 16-Bit, 4:2:2 15 14 13 12 11 10 YCrCb[7:0]OUT Y[7:0]OUT Data Port Pins P[15:0] 9 8 7 6 5 4 3 2 1 0
CrCb[7:0]OUT
Table 97. ADV7180 LFCSP-40 P7 to P0 Output/Input Pin Mapping
Format and Mode Video Out, 8-Bit, 4:2:2 7 6 5 Data Port Pins P[7:0] 4 3 YCrCb[7:0]OUT 2 1 0
Table 98. ADV7180 Standard Definition Pixel Port Modes
OF_SEL[3:0] 0000 to 0001 0010 0011 (Default) 0100 to 1111 Format Reserved 16-bit @ LLC2 4:2:2 8-bit @ LLC1 4:2:2 (default) Reserved ADV7180 LQFP-64 P[15: 0] ADV7180 LFCSP-40 P[15:8] P[7: 0] P[7: 0] Reserved, do not use Y[7:0] CrCb[7:0] Not valid YCrCb[7:0] Three-state YCrCb[7:0] Reserved, do not use
Rev. A | Page 72 of 112
ADV7180 GPO CONTROL
The ADV7180 LQFP-64 has four general-purpose outputs (GPO). These outputs allow the user to control other devices in a system via the I2C port of the ADV7180 LQFP-64. The ADV7180 LFCSP-40 does not have GPO pins.
GPO_Enable, General Purpose Output Enable, Address 0x59[4] Table 99. General-Purpose Output Truth Table
GPO_Enable 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPO[3:0] XXXX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GPO3 Z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GPO2 Z 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GPO1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GPO0 Z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
When GPO_Enable is set to 0, all four GPO pins are three-stated. When GPO_Enable is set to 1, all four GPO pins are in a driven state. The polarity output from each GPO is controlled by GPO[3:0].
GPO[3:0], General Purpose Outputs, Address 0x59 [3:0]
Individual control of the four GPO ports is achieved using GPO[3:0]. GPO_Enable must be set to 1 for the GPO pins to become active.
GPO[0]
When GPO[0] is set to 0, a Logic Level 0 is output from the GPO0 pin [Pin 13] When GPO[0] is set to 1, a Logic Level 1 is output from the GPO0 pin.
GPO[1]
When GPO[1] is set to 0, a Logic Level 0 is output from the GPO1 pin [Pin 12]. When GPO[1] is set to 1, a Logic Level 1 is output from the GPO1 pin.
GPO[2]
When GPO[2] is set to 0, a Logic Level 0 is output from the GPO2 pin [Pin 56]. When GPO[2] is set to 1, a Logic Level 1 is output from the GPO2 pin.
GPO[3]
When GPO[3] is set to 0, a Logic Level 0 is output from the GPO3 pin [Pin 55]. When GPO[3] is set to 1, a Logic Level 1 is output from the GPO3 pin.
Rev. A | Page 73 of 112
ADV7180 MPU PORT DESCRIPTION
The ADV7180 supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7180 and the system I2C master controller. Each slave device is recognized by a unique address. The ADV7180 I2C port allows the user to set up and configure the decoder and to read back captured VBI data. The ADV7180 has four possible slave addresses for both read and write operations, depending on the logic level of the ALSB pin. The four unique addresses are shown in Table 100. The ADV7180 ALSB pin controls Bit 1 of the slave address. By altering the ALSB, it is possible to control two ADV7180s in an application without having the conflict of using the same slave address. The LSB (Bit 0) sets either a read or write operation. Logic 1 corresponds to a read operation; Logic 0 corresponds to a write operation.
Table 100. I2C Address for ADV7180
ALSB 0 0 1 1 R/W 0 1 0 1 Slave Address 0x40 0x41 0x42 0x43
first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV7180 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit address plus the R/W bit. The device has 249 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7180 does not issue an acknowledge and returns to the idle condition. In auto-increment mode, if the user exceeds the highest subaddress, the following action is taken: * In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register. A no acknowledge is issued by the ADV7180, and the part returns to the idle condition.
To control the device on the bus, a specific protocol must be followed. First, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on SDA while SCLK remains high. This indicates that an address/ data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCLK lines for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the
*
SDATA
1-7
8
9
1-7
8
9
1-7 DATA
8
9 ACK
START ADDR R/W ACK SUBADDRESS ACK
STOP
Figure 48. Bus Data Transfer
WRITE SEQUENCE
S SLAVE ADDR
A(S) LSB = 0
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER
Figure 49. Read and Write Sequence
Rev. A | Page 74 of 112
05700-045
READ SEQUENCE
S SLAVE ADDR
A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
05700-044
SCLOCK
S
P
DATA
A(M) P
ADV7180
REGISTER ACCESS
The MPU can write to or read from all of the ADV7180 registers except the subaddress register, which is write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. Then a read/write operation is performed from or to the target address, which increments to the next address until a stop command on the bus is performed.
Register Select (SR7 to SR0)
These bits are set up to point to the required starting address.
I2C SEQUENCER
An I2C sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more I2C registers, for example, HSB [11:0]. When such a parameter is changed using two or more I2C write operations, the parameter may hold an invalid value for the time between the first I2C being completed and the last I2C being completed. In other words, the top bits of the parameter may hold the new value while the remaining bits of the parameter still hold the previous value. To avoid this problem, the I2C sequencer holds the updated bits of the parameter in local memory, and all bits of the parameter are updated together once the last register write operation has completed. The correct operation of the I2C sequencer relies on the following: * All I2C registers for the parameter in question must be written to in order of ascending addresses. For example, for HSB[10:0], write to Address 0x34 first, followed by 0x35, and so on. No other I2C can take place between the two (or more) I2C writes for the sequence. For example, for HSB[10:0], write to Address 0x34 first, immediately followed by 0x35, and so on.
REGISTER PROGRAMMING
The following sections describe the configuration for each register. The communication register is an 8-bit, write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to or from which register the operation takes place. Table 101 lists the various operations under the control of the subaddress register for the control port.
SUB_USR_EN, Address 0x0E [5]
This bit splits the register map at Register 0x40.
USER MAP COMMON I2C SPACE ADDRESS 0x00 0x3F USER SUB MAP
*
ADDRESS 0x0E BIT 5 = 0b ADDRESS 0x0E BIT 5 = 1b
NORMAL REGISTER SPACE
INTERRUPT AND VDP REGISTER SPACE
Figure 50. Register Access--User Map and User Sub Map
Rev. A | Page 75 of 112
05700-050
I2C SPACE ADDRESS 0x40 0xFF
I2C SPACE ADDRESS 0x40 0x9C
ADV7180 I2C REGISTER MAPS
Table 101. Main Register Map Details
Address Dec Hex Register Name 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 29 39 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 61 65 72 73 74 75 76 77 78 80 81 88 89 00 01 03 04 05 06 07 08 09 0A 0B 0C Input Control Video Selection Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y RW BRI[7] RW HUE[7] RW DEF_Y[5] RW DEF_C[7] RW RESET R R R R RW RW RW CSFM[2] RW WYSFMOVR RW RW TRI_LLC RW SWPC RW RW W W W W RW RW VSBHO RW VSEHO VSBHE VSEHE HSB[10] HSB[6] HSE[6] CTAPSN[0] CTAPSP[0] HSB[9] HSB[5] HSE[5] PVS CCMN[2] CCMP[2] CCMN[1] CCMP[1] HSB[8] HSB[4] HSE[4] HSB[3] HSE[3] PF CCMN[0] CCMP[0] MUX_0_PD CKILLTHR[2] SFL_INV GDECEL[14] GDECEL[6] GDECOL[14] GDECOL[6] GDECEL[13] GDECEL[5] GDECOL[13] GDECOL[5] DNR_EN CTI_C_TH[6] DNR_TH[6] SRLS CTI_C_TH[5] DNR_TH[5] COL[2] CTI_C_TH[4] DNR_TH[4] COL[1] GDECEL[12] GDECEL[4] GDECOL[12] GDECOL[4] GDECEL[11] GDECEL[3] GDECOL[11] GDECOL[3] CTI_AB.1 CTI_C_TH[3] DNR_TH[3] COL[0] GDECEL[10] GDECEL[2] GDECOL[10] GDECOL[2] CTI_AB.0 CTI_C_TH[2] DNR_TH[2] CIL[2] ADC sampling control GPO_Enable LLC_PAD_ SEL_MAN CCAP1[7] CCAP1[6] LLC_PAD_ SEL[1] CCAP1[5] LLC_PAD_ SEL[0] CCAPD CCAP1[4] CCAP1[3] CCAP1[2] CCAP1[1] CCAP1[0] - - GPO[3] GPO[2] GPO[1] GDECEL[9] GDECEL[1] GDECOL[9] GDECOL[1] CTI_AB_EN CTI_C_TH[1] DNR_TH[1] CIL[1] GDECEL[8] GDECEL[0] GDECOL[8] GDECOL[0] GDECAD CTI_EN CTI_C_TH[0] DNR_TH[0] CIL[0] VS/FIELD GPO[0] CKILLTHR[1] CKILLTHR[0] YCMN[2] YCMP[2] MUX_1_PD YCMN[1] YCMP[1] MUX_2_PD HSE[10] HSB[2] HSE[2] HSE[9] HSB[1] HSE[1] HSE[8] HSB[0] HSE[0] PCLK YCMN[0] YCMP[0] MUX PDN Override CAGT[1] CMG[7] LAGT[1] LMG.7 EN28XTAL AUTO_PDC_EN CTA[2] CKE LAGC[2] CAGT[0] CMG[6] LAGT[0] LMG[6] LMG[5] LMG[4] NEWAVMODE CMG[5] CMG[4] LAGC[1] LAGC[0] CMG[11] CMG[3] LMG[11] LMG[3] HVSTIM CMG[10] CMG[2] LMG[10] LMG[2] CAGC[1] CMG[9] CMG[1] LMG[9] LMG[1] CTA[1] CTA[0] LTA[1] LTA[0] PW_UPD CAGC[0] CMG[8] CMG[0] LMG[8] LMG[0] DCT[1] CSFM[1] DCT[0] CSFM[0] YSFM[4] WYSFM[4] YSFM[3] WYSFM[3] NSFSEL[1] YSFM[2] WYSFM[2] NSFSEL[0] YSFM[1] WYSFM[1] PSFSEL[1] YSFM[0] WYSFM[0] PSFSEL[0] PAL_SW_LOCK INTERLACED COL_KILL IDENT[7] IDENT[6] BRI[6] HUE[6] DEF_Y[4] DEF_C[6] BRI[5] HUE[5] DEF_Y[3] DEF_C[5] SUB_USR_EN PWRDWN AD_RESULT[2] AD_RESULT[1] AD_RESULT[0] FOLLOW_PW IDENT[5] FSC NSTD STD FLD LEN IDENT[4] LL NSTD CCLEN IDENT[3] MV AGC DET PDBP FSC_LOCK IDENT[2] MV PS DET SD_OP_50Hz LOST_LOCK IDENT[1] MVCS T3 GEMD IN_LOCK IDENT[0] MVCS DET INST_HLOCK BRI[4] HUE[4] DEF_Y[2] DEF_C[4] BRI[3] HUE[3] DEF_Y[1] DEF_C[3] BRI[2] HUE[2] DEF_Y[0] DEF_C[2] BRI[1] HUE[1] DEF_VAL_ AUTO_EN DEF_C[1] BRI[0] HUE[0] DEF_VAL_EN DEF_C[0] 00000000 00 00000000 00 00110110 36 01111100 7C 00000000 00 00000000 00 ------------00011011 1B RW AD_SEC525_EN AD_SECAM_EN AD_N443_EN AD_P60_EN RW CON[7] CON[6] CON[5] CON[4] AD_PALN_EN AD_PALM_EN CON[3] CON[2] AD_NTSC_EN AD_PAL_EN CON[1] CON[0] 01111111 7F 10000000 80 RW 7 RW VID_SEL[3] RW RW VBI_EN 6 VID_SEL[2] ENHSPLL TOD 5 VID_SEL[1] BETACAM OF_SEL[3] OF_SEL[2] 4 VID_SEL[0] 3 INSEL[3] ENVSPROC OF_SEL[1] TIM_OE OF_SEL[0] BL_C_VBI EN_SFL_PIN SD_DUP_AV RANGE 2 INSEL[2] 1 INSEL[1] 0 INSEL[0] Reset Value (Hex) 00000000 00 11001000 C8 00001100 0C 01xx0101 45
Extended Output Control RW BT.656-4
0D Default Value C 0E 0F 10 11 12 13 14 15 16 17 18 19 27 2B 2C 2E 2F 30 31 32 33 34 35 36 37 38 39 3A ADI Control 1 Power Management Status 1 IDENT Status 2 Status 3 Analog Clamp Control Digital Clamp Control Reserved Shaping Filter Control 1 Shaping Filter Control 2 Comb Filter Control Pixel Delay Control Misc Gain Control AGC Mode Control Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 VSYNC Field Control 1 VSYNC Field Control 2 VSYNC Field Control 3
FREE_RUN_ACT CVBS
00010010 12 0000xxxx 00 00000001 01 10010011 93 11110001 F1 01000xxx 40 01011000 58 11100001 E1 10101110 AE 11110100 F4 00000000 00 1111xxxx F0 xxxxxxxx 00 00010010 12 01000001 41 10000100 84 00000000 00 00000010 02 00000000 00 00000001 01 10000000 80 11000000 C0 00010000 10 01110010 B2 00000001 01 00000000 00 00000000 00 00000000 00 00000000 00 xxxx0000 00 11101111 EF 00001000 08 00001000 08 00100100 24 00000000 00 00000000 00 00000000 00
1D ADI Control 2
2D Chroma Gain Control 1
HSYNC Position Control 1 RW HSYNC Position Control 2 RW HSB.7 HSYNC Position Control 3 RW HSE.7 Polarity NTSC Comb Control PAL Comb Control ADC Control RW PHS RW CTAPSN[1] RW CTAPSP[1] RW
3D Manual Window Control RW 41 48 49 4A 4B 4C 4E 50 51 58 59 Resample Control Gemstar Control 1 Gemstar Control 2 Gemstar Control 3 Gemstar Control 4 Gemstar Control 5 CTI DNR Control 2 CTI DNR Control 4 Lock Count VS/FIELD Pin Control 1 General-Purpose O/P 2 Free-Run Line Length 1 VBI INFO CCAP 1 RW RW GDECEL[15] RW GDECEL[7] RW GDECOL[15] RW GDECOL[7] RW RW RW CTI_C_TH[7] RW DNR_TH[7] RW FSCLE RW RW W R R
4D CTI DNR Control 1
143 8F 144 90 153 99
Rev. A | Page 76 of 112
ADV7180
Address Dec Hex Register Name 154 9A 155 9B 156 9C 178 B2 195 C3 196 C4 CCAP 2 Letterbox 1 Letterbox 2 CRC ADC Switch 1 ADC Switch 2 RW 7 R R R R W RW MUX1[3] RW MAN_MUX_EN RW RW LB_SL[3] R R ST_NOISE[7] ST_NOISE.6 ST_NOISE[5] ST_NOISE[4] LB_SL.2 LB_SL[1] LB_TH[4] LB_SL[0] MUX1[2] MUX1[1] MUX1[0] MUX0[3] MUX2[3] LB_TH[3] LB_EL[3] ST_NOISE[3] CCAP2[7] LB_LCT[7] LB_LCM[7] LB_LCB[7] 6 CCAP2[6] LB_LCT[6] LB_LCM[6] LB_LCB[6] 5 CCAP2[5] LB_LCT[5] LB_LCM[5] LB_LCB[5] 4 CCAP2[4] LB_LCT[4] LB_LCM[4] LB_LCB[4] 3 CCAP2[3] LB_LCT[3] LB_LCM[3] LB_LCB[3] 2 CCAP2[2] LB_LCT[2] LB_LCM[2] LB_LCB[2] CRC_ENABLE MUX0[2] MUX2[2] LB_TH[2] LB_EL[2] ST_NOISE[2] MUX0[1] MUX2[1] LB_TH[1] LB_EL[1] ST_NOISE[9] ST_NOISE[1] MUX0[0] MUX2[0] LB_TH[0] LB_EL[0] ST_NOISE[8] ST_NOISE[0] 1 CCAP2[1] LB_LCT[1] LB_LCM[1] LB_LCB[1] 0 CCAP2[0] LB_LCT[0] LB_LCM[0] LB_LCB[0] Reset Value - - - - (Hex) - - - -
157 9D Letterbox 3
00011100 1C xxxxxxxx 00 0xxxxxxx 00 10101100 AC 01001100 4C - - - -
220 DC Letterbox Control 1 221 DD Letterbox Control 2 222 DE 223 DF 224 E0 225 E1 226 E2 227 E3 228 E4 229 E5 230 E6 231 E7 232 E8 233 E9 234 EA 235 EB 236 EC 243 F3 244 F4 248 F8 249 F9 251 FB 252 FC
1 2
ST Noise Readback 1 ST Noise Readback 2 Reserved SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Vblank Control 1 Vblank Control 2 AFE_CONTROL 1 Drive Strength IF Comp Control VS Mode Control Peaking Control Coring Threshold
ST_NOISE_VLD ST_NOISE[10]
RW SD_OFF_CB[7] SD_OFF_CB[6] SD_OFF_CB[5] SD_OFF_CB[4] SD_OFF_CB[3] SD_OFF_CB[2] RW SD_OFF_CR[7] SD_OFF_CR[6] SD_OFF_CR[5] SD_OFF_CR[4] SD_OFF_CR[3] SD_OFF_CR[2] RW SD_SAT_CB[7] RW SD_SAT_CR[7] RW NVBEGDELO RW NVENDDELO RW NFTOGDELO RW PVBEGDELO RW PVENDDELO RW PFTOGDELO RW NVBIOLCM[1] RW NVBIOCCM[1] RW RW RW RW RW PEAKING_ GAIN[7] RW DNR_TH2[7] PEAKING_ GAIN[6] DNR_TH2[6] PEAKING_ GAIN[5] DNR_TH2[5] PEAKING_ GAIN[4] DNR_TH2[4] VS_COAST_ MODE[1] PEAKING_ GAIN[3] DNR_TH2[3] DR_STR[1] DR_STR[0] SD_SAT_CB[6] SD_SAT_CB[5] SD_SAT_CB[4] SD_SAT_CR[6] SD_SAT_CR[5] SD_SAT_CR[4] NVBEGDELE NVENDDELE NFTOGDELE PVBEGDELE PVENDDELE PFTOGDELE NVBIOLCM[0] NVBIOCCM[0] NVBEGSIGN NVENDSIGN NFTOGSIGN PVBEGSIGN PVENDSIGN PFTOGSIGN NVBIELCM[1] NVBEG[4] NVEND[4] NFTOG[4] PVBEG[4] PVEND[4] PFTOG[4] NVBIELCM[0] SD_SAT_CB[3] SD_SAT_CB[2] SD_SAT_CR[3] SD_SAT_CR[2] NVBEG[3] NVEND[3] NFTOG[3] PVBEG[3] PVEND[3] PFTOG[3] PVBIOLCM.1 PVBIOCCM.1 AA_FILT_ MAN_OVR DR_STR_C[1] NVBEG[2] NVEND[2] NFTOG[2] PVBEG[2] PVEND[2] PFTOG[2] PVBIOLCM.0 PVBIOCCM.0 AA_FILT_EN[2] DR_STR_C[0] IFFILTSEL[2] VS_COAST_ MODE[0] PEAKING_ GAIN[2] DNR_TH2[2]
SD_OFF_CB[1] SD_OFF_CB[0] SD_OFF_CR[1] SD_OFF_CR[0] SD_SAT_CB[1] SD_SAT_CB[0] SD_SAT_CR[1] SD_SAT_CR[0] NVBEG[1] NVEND[1] NFTOG[1] PVBEG[1] PVEND[1] PFTOG[1] PVBIELCM.1 PVBIECCM.1 NVBEG[0] NVEND[0] NFTOG[0] PVBEG[0] PVEND[0] PFTOG[0] PVBIELCM.0 PVBIECCM.0
10000000 80 10000000 80 10000000 80 10000000 80 00100101 25 00000100 04 01100011 63 01100101 65 00010100 14 01100011 63 01010101 55 01010101 55 00000000 00 xx010101 15 00000000 00 00000011 03 01000000 40 00000100 04
NVBIECCM[1] NVBIECCM[0]
AA_FILT_EN[1] AA_FILT_EN[0] DR_STR_S[1] IFFILTSEL[1] EXTEND_VS_ MIN_FREQ PEAKING_ GAIN[1] DNR_TH2[1] DR_STR_S[0] IFFILTSEL[0] EXTEND_VS_ MAX_FREQ PEAKING_ GAIN[0] DNR_TH2[0]
This feature applies to the ADV7180BCPZ 40-lead only because VS or field are shared on a single pin (Pin 37). This feature applies to the ADV7180BSTZ 64-lead only.
Table 102. Interrupt System Register Map Details 1
Address Dec 64 66 67 68 69 70 71 72 Hex 40 42 43 44 45 46 47 48 Register Name Interrupt Config. 1 Interrupt Status 1 Interrupt Clear 1 Interrupt Mask 1 Raw Status 1 Interrupt Status 2 Interrupt Clear 2 Interrupt Mask 2 Raw Status 2 Interrupt Status 3 Interrupt Clear 3 Interrupt Mask 3 Interrupt Status 4 R/W RW R W RW R R W RW MPU_STIM_I NTRQ MPU_STIM_ INTRQ_Q MPU_STIM_ INTRQ_CLR MPU_STIM_ INTRQ_MSKB 7 INTRQ_DUR_ SEL[1] 6 INTRQ_DUR_ SEL[0] MV_PS_CS_Q MV_PS_CS_ CLR MV_PS_CS_ MSKB 5 MV_INTRQ_ SEL[1] SD_FR_ CHNG_Q SD_FR_ CHNG_CLR SD_FR_ CHNG_MSKB EVEN_FIELD SD_FIELD_ CHNGD_Q SD_FIELD_ CHNGD_CLR SD_FIELD_ CHNGD_MSK B SCM_LOCK PAL_SW_LK_ CHNG_Q PAL_SW_LK_ CHNG_CLR PAL_SW_LK_ CHNG_MSKB VDP_VITC_Q SCM_LOCK_ CHNG_Q SCM_LOCK_ CHNG_CLR SCM_LOCK_ CHNG_MSKB VDP_GS_ VPS_PDC_ UTC_CHNG_ Q VDP_GS_ VPS_PDC_ UTC_CHNG_ CLR SD_AD_ CHNG_Q SD_AD_ CHNG_CLR SD_AD_ CHNG_MSKB SD_H_LOCK SD_H_LOCK_ CHNG_Q SD_H_LOCK_ CHNG_CLR SD_H_LOCK_ CHNG_MSKB VDP_CGMS_ WSS_ CHNGD_Q VDP_CGMS_ WSS_CHNGD _CLR GEMD_Q GEMD_CLR GEMD_MSKB 4 MV_INTRQ_ SEL[0] 3 2 MPU_STIM_ INTRQ 1 INTRQ_OP_ SEL[1] SD_UNLOCK _Q SD_UNLOCK_ CLR SD_UNLOCK_ MSKB 0 INTRQ_OP_SE L[0] SD_LOCK_Q SD_LOCK_ CLR SD_LOCK_ MSKB CCAPD CCAPD_Q CCAPD_CLR CCAPD_ MSKB SD_OP_50Hz SD_OP_ CHNG_Q SD_OP_ CHNG_CLR SD_OP_ CHNG_MSKB VDP_CCAPD_ Q Reset Value 0001x000 - x0000000 x0000000 - - 0xx00000 0xx00000 (Hex) 10 - 00 00 - - 00 00
73 74 75 76 78
49 4A 4B 4C 4E
R R W RW R
SD_V_LOCK SD_V_LOCK_ CHNG_Q SD_V_LOCK_ CHNG_CLR SD_V_LOCK_ CHNG_MSKB
- - xx000000 xx000000 -
- - 00 00 -
79
4F
Interrupt Clear 4
W
VDP_VITC_ CLR
VDP_CCAPD_ CLR
00x0x0x0
00
Rev. A | Page 77 of 112
ADV7180
Address Dec 80 Hex 50 Register Name Interrupt Mask 4 R/W RW 7 6 VDP_VITC_ MSKB 5 4 VDP_GS_ VPS_PDC_ UTC_CHNG_ MSKB WST_PKT_ DECODE_ DISABLE AUTO_ DETECT_GS_ TYPE ADF_ENABLE DUPLICATE_ ADF MAN_LINE_ PGM VBI_DATA_ P6_N23[3] VBI_DATA_ P7_N24[3] VBI_DATA_ P8_N25[3] VBI_DATA_ P9[3] VBI_DATA_ P10[3] VBI_DATA_ P11[3] VBI_DATA_ P12_N10[3] VBI_DATA_ P13_N11[3] VBI_DATA_ P14_N12[3] VBI_DATA_ P15_N13[3] VBI_DATA_ P16_N14[3] VBI_DATA_ P17_N15[3] VBI_DATA_ P18_N16[3] VBI_DATA_ P19_N17[3] VBI_DATA_ P20_N18[3] VBI_DATA_ P21_N19[3] VBI_DATA_ P22_N20[3] VBI_DATA_ P23_N21[3] VBI_DATA_ P24_N22[3] VBI_DATA_ P6_N23[2] VBI_DATA_ P7_N24[2] VBI_DATA_ P8_N25[2] VBI_DATA_ P9[2] VBI_DATA_ P10[2] VBI_DATA_ P11[2] VBI_DATA_ P12_N10[2] VBI_DATA_ P13_N11[2] VBI_DATA_ P14_N12[2] VBI_DATA_ P15_N13[2] VBI_DATA_ P16_N14[2] VBI_DATA_ P17_N15[2] VBI_DATA_ P18_N16[2] VBI_DATA_ P19_N17[2] VBI_DATA_ P20_N18[2] VBI_DATA_ P21_N19[2] VBI_DATA_ P22_N20[2] VBI_DATA_ P23_N21[2] VBI_DATA_ P24_N22[2] VITC_CLEAR VBI_DATA_ P6_N23[1] VBI_DATA_ P7_N24[1] VBI_DATA_ P8_N25[1] VBI_DATA_ P9[1] VBI_DATA_ P10.1 VBI_DATA_ P11[1] VBI_DATA_ P12_N10[1] VBI_DATA_ P13_N11[1] VBI_DATA_ P14_N12[1] VBI_DATA_ P15_N13[1] VBI_DATA_ P16_N14[1] VBI_DATA_ P17_N15[1] VBI_DATA_ P18_N16[1] VBI_DATA_ P19_N17[1] VBI_DATA_ P20_N18[1] VBI_DATA_ P21_N19[1] VBI_DATA_ P22_N20[1] VBI_DATA_ P23_N21[1] VBI_DATA_ P24_N22[1] VBI_DATA_ P6_N23[0] VBI_DATA_ P7_N24[0] VBI_DATA_ P8_N25[0] VBI_DATA_ P9[0] VBI_DATA_ P10[0] VBI_DATA_ P11[0] VBI_DATA_ P12_N10[0] VBI_DATA_ P13_N11[0] VBI_DATA_ P14_N12[0] VBI_DATA_ P15_N13[0] VBI_DATA_ P16_N14[0] VBI_DATA_ P17_N15[0] VBI_DATA_ P18_N16[0] VBI_DATA_ P19_N17[0] VBI_DATA_ P20_N18[0] VBI_DATA_ P21_N19[0] VBI_DATA_ P22_N20[0] VBI_DATA_ P23_N21[0] VBI_DATA_ P24_N22[0] GS_PDC_ VPS_UTC_ CLEAR GS_DATA_ TYPE CCAP_ BYTE_1[5] CCAP_ BYTE_2[5] GS_PDC_ VPS_UTC_ AVL CCAP_ BYTE_1[4] CCAP_ BYTE_2[4] CCAP_ BYTE_1[3] CCAP_ BYTE_2[3] CGMS_ CRC[5] CGMS_ CRC[1] CGMS_ WSS[7] GS_VPS_ PDC_UTC_ BYTE_0[7] GS_VPS_ PDC_UTC_ BYTE_1[7] GS_VPS_ PDC_UTC_ BYTE_2[7] CGMS_ CRC[0] CGMS_ WSS[6] GS_VPS_ PDC_UTC_ BYTE_0[6] GS_VPS_ PDC_UTC_ BYTE_1[6] GS_VPS_ PDC_UTC_ BYTE_2[6] CGMS_ WSS[13] CGMS_ WSS[5] GS_VPS_ PDC_UTC_ BYTE_0[5] GS_VPS_ PDC_UTC_ BYTE_1[5] GS_VPS_ PDC_UTC_ BYTE_2[5] CGMS_ WSS[12] CGMS_ WSS[4] GS_VPS_ PDC_UTC_ BYTE_0[4] GS_VPS_ PDC_UTC_ BYTE_1[4] GS_VPS_ PDC_UTC_ BYTE_2[4] CGMS_ WSS[11] CGMS_ WSS[3] GS_VPS_ PDC_UTC_ BYTE_0[3] GS_VPS_ PDC_UTC_ BYTE_1[3] GS_VPS_ PDC_UTC_ BYTE_2[3] ADF_MODE[1] ADF_MODE[0] ADF_SDID[5] ADF_DID[4] ADF_SDID[4] ADF_DID[3] ADF_SDID[3] VBI_DATA_ P318[3] VBI_DATA_ P319_N286[3] VBI_DATA_ P320_N287[3] VBI_DATA_ P321_N288[3] VBI_DATA_ P322[3] VBI_DATA_ P323[3] VBI_DATA_ P324_N272[3] VBI_DATA_ P325_N273[3] VBI_DATA_ P326_N274[3] VBI_DATA_ P327_N275[3] VBI_DATA_ P328_N276[3] VBI_DATA_ P329_N277[3] VBI_DATA_ P330_N278[3] VBI_DATA_ P331_N279[3] VBI_DATA_ P332_N280[3] VBI_DATA_ P333_N281[3] VBI_DATA_ P334_N282[3] VBI_DATA_ P335_N283[3] VBI_DATA_ P336_N284[3] VBI_DATA_ P337_N285[3] ADF_DID[2] ADF_SDID[2] VBI_DATA_ P318[2] VBI_DATA_ P319_N286[2] VBI_DATA_ P320_N287[2] VBI_DATA_ P321_N288[2] VBI_DATA_ P322[2] VBI_DATA_ P323[2] VBI_DATA_ P324_N272[2] VBI_DATA_ P325_N273[2] VBI_DATA_ P326_N274[2] VBI_DATA_ P327_N275[2] VBI_DATA_ P328_N276[2] VBI_DATA_ P329_N277[2] VBI_DATA_ P330_N278[2] VBI_DATA_ P331_N279[2] VBI_DATA_ P332_N280[2] VBI_DATA_ P333_N281[2] VBI_DATA_ P334_N282[2] VBI_DATA_ P335_N283[2] VBI_DATA_ P336_N284[2] VBI_DATA_ P337_N285[2] CGMS_WSS_ CLEAR CGMS_WSS_ AVL CCAP_ BYTE_1[2] CCAP_ BYTE_2[2] CGMS_ CRC[4] CGMS_ WSS[10] CGMS_ WSS[2] GS_VPS_ PDC_UTC_ BYTE_0[2] GS_VPS_ PDC_UTC_ BYTE_1[2] GS_VPS_ PDC_UTC_ BYTE_2[2] CC_EVEN_ FIELD CCAP_ BYTE_1[1] CCAP_ BYTE_2[1] CGMS_ CRC[3] CGMS_ WSS[9] CGMS_ WSS[1] GS_VPS_ PDC_UTC_ BYTE_0[1] GS_VPS_ PDC_UTC_ BYTE_1[1] GS_VPS_ PDC_UTC_ BYTE_2[1] ADF_DID[1] ADF_SDID[1] VBI_DATA_ P318[1] VBI_DATA_ P319_N286[1] VBI_DATA_ P320_N287[1] VBI_DATA_ P321_N288[1] VBI_DATA_ P322[1] VBI_DATA_ P323[1] VBI_DATA_ P324_N272[1] VBI_DATA_ P325_N273[1] VBI_DATA_ P326_N274[1] VBI_DATA_ P327_N275[1] VBI_DATA_ P328_N276[1] VBI_DATA_ P329_N277[1] VBI_DATA_ P330_N278[1] VBI_DATA_ P331_N279[1] VBI_DATA_ P332_N280[1] VBI_DATA_ P333_N281[1] VBI_DATA_ P334_N282[1] VBI_DATA_P 335_N283[1] VBI_DATA_ P336_N284[1] VBI_DATA_ P337_N285[1] ADF_DID[0] ADF_SDID[0] VBI_DATA_ P318[0] VBI_DATA_ P319_N286[0] VBI_DATA_ P320_N287[0] VBI_DATA_ P321_N288[0] VBI_DATA_ P322[0] VBI_DATA_ P323[0] VBI_DATA_ P324_N272[0] VBI_DATA_ P325_N273[0] VBI_DATA_ P326_N274[0] VBI_DATA_ P327_N275[0] VBI_DATA_ P328_N276[0] VBI_DATA_ P329_N277[0] VBI_DATA_ P330_N278[0] VBI_DATA_ P331_N279[0] VBI_DATA_ P332_N280[0] VBI_DATA_ P333_N281[0] VBI_DATA_ P334_N282[0] VBI_DATA_ P335_N283[0] VBI_DATA_ P336_N284[0] VBI_DATA_ P337_N285[0] CC_CLEAR 3 2 VDP_CGMS_ WSS_CHNGD_ MSKB VDP_TTXT_ TYPE_MAN_ ENABLE VDP_TTXT_ TYPE_MAN[1] 1 0 VDP_CCAPD_ MSKB Reset Value 00x0x0x0 (Hex) 00
96
60
VDP_Config_1
RW
VDP_TTXT_ TYPE_MAN[0]
10001000
88
97
61
VDP_Config_2
RW
0001xx00
10
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78
VDP_ADF_ Config_1 VDP_ADF_ Config_2 VDP_LINE_00E VDP_LINE_00F VDP_LINE_010 VDP_LINE_011 VDP_LINE_012 VDP_LINE_013 VDP_LINE_014 VDP_LINE_015 VDP_LINE_016 VDP_LINE_017 VDP_LINE_018 VDP_LINE_019 VDP_LINE_01A VDP_LINE_01B VDP_LINE_01C VDP_LINE_01D VDP_LINE_01E VDP_LINE_01F VDP_LINE_020 VDP_LINE_021 VDP_STATUS_ CLEAR VDP_STATUS
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W
00010101 0x101010 0xxx0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
15 2A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
120
78
R
TTXT_AVL
VITC_AVL
CC_AVL
-
-
121 122 125 126 127 132
79 7A 7D 7E 7F 84
VDP_CCAP_ DATA_0 VDP_CCAP_ DATA_1 VDP_CGMS_ WSS_DATA_0 VDP_CGMS_ WSS_DATA_1 VDP_CGMS_ WSS_ DATA_2 VDP_GS_VPS_ PDC_UTC_0 VDP_GS_VPS_ PDC_UTC_1 VDP_GS_VPS_ PDC_UTC_2
R R R R R R
CCAP_ BYTE_1[7] CCAP_ BYTE_2[7]
CCAP_ BYTE_1[6] CCAP_ BYTE_2[6]
CCAP_ BYTE_1[0] CCAP_ BYTE_2[0] CGMS_ CRC[2] CGMS_ WSS[8] CGMS_ WSS[0] GS_VPS_ PDC_UTC_ BYTE_0[0] GS_VPS_ PDC_UTC_ BYTE_1[0] GS_VPS_ PDC_UTC_ BYTE_2[0]
- - - - - -
- - - - - -
133
85
R
-
-
134
86
R
-
-
Rev. A | Page 78 of 112
ADV7180
Address Dec 135 Hex 87 Register Name VDP_GS_VPS_ PDC_UTC_3 VDP_VPS_ PDC_UTC_4 VDP_VPS_ PDC_UTC_5 VDP_VPS_ PDC_UTC_6 VDP_VPS_ PDC_UTC_7 VDP_VPS_ PDC_UTC_8 VDP_VPS_ PDC_UTC_9 VDP_VPS_ PDC_UTC_10 VDP_VPS_ PDC_UTC_11 VDP_VPS_ PDC_UTC_12 VDP_VITC_ DATA_0 VDP_VITC_ DATA_1 VDP_VITC_ DATA_2 VDP_VITC_ DATA_3 VDP_VITC_ DATA_4 VDP_VITC_ DATA_5 VDP_VITC_ DATA_6 VDP_VITC_ DATA_7 VDP_VITC_ DATA_8 VDP_VITC_ CALC_CRC VDP_OUTPUT_ SEL R/W R 7 GS_VPS_ PDC_UTC_ BYTE_3[7] VPS_ PDC_UTC_ BYTE_4[7] VPS_ PDC_UTC_ BYTE_5[7] VPS_ PDC_UTC_ BYTE_6[7] VPS_ PDC_UTC_ BYTE_7[7] VPS_ PDC_UTC_ BYTE_8[7] VPS_ PDC_UTC_ BYTE_9[7] VPS_ PDC_UTC_ BYTE_10[7] VPS_ PDC_UTC_ BYTE_11[7] VPS_ PDC_UTC_ BYTE_12[7] VITC_ DATA_0[7] VITC_ DATA_1[7] VITC_ DATA_2[7] VITC_ DATA_3[7] VITC_ DATA_4[7] VITC_ DATA_5[7] VITC_ DATA_6[7] VITC_ DATA_7[7] VITC_ DATA_8[7] VITC_CRC[7] I C_GS_ VPS_PDC_ UTC[1]
2
Reset 6 GS_VPS_ PDC_UTC_ BYTE_3.6 VPS_ PDC_UTC_ BYTE_4[6] VPS_ PDC_UTC_ BYTE_5[6] VPS_ PDC_UTC_ BYTE_6[6] VPS_ PDC_UTC_ BYTE_7[6] VPS_ PDC_UTC_ BYTE_8[6] VPS_ PDC_UTC_ BYTE_9[6] VPS_ PDC_UTC_ BYTE_10[6] VPS_ PDC_UTC_ BYTE_11[6] VPS_ PDC_UTC_ BYTE_12[6] VITC_ DATA_0[6] VITC_ DATA_1[6] VITC_ DATA_2[6] VITC_ DATA_3[6] VITC_ DATA_4[6] VITC_ DATA_5[6] VITC_ DATA_6[6] VITC_ DATA_7[6] VITC_ DATA_8[6] VITC_CRC[6] I C_GS_ VPS_PDC_ UTC[0]
2
5 GS_VPS_ PDC_UTC_ BYTE_3.5 VPS_ PDC_UTC_ BYTE_4[5] VPS_ PDC_UTC_ BYTE_5[5] VPS_ PDC_UTC_ BYTE_6[5] VPS_ PDC_UTC_ BYTE_7[5] VPS_ PDC_UTC_ BYTE_8[5] VPS_ PDC_UTC_ BYTE_9[5] VPS_ PDC_UTC_ BYTE_10[5] VPS_ PDC_UTC_ BYTE_11[5] VPS_ PDC_UTC_ BYTE_12[5] VITC_ DATA_0[5] VITC_ DATA_1[5] VITC_ DATA_2[5] VITC_ DATA_3[5] VITC_ DATA_4[5] VITC_ DATA_5[5] VITC_ DATA_6[5] VITC_ DATA_7[5] VITC_ DATA_8[5] VITC_CRC.5 GS_VPS_ PDC_UTC_ CB_CHANGE
4 GS_VPS_ PDC_UTC_ BYTE_3.4 VPS_ PDC_UTC_ BYTE_4[4] VPS_ PDC_UTC_ BYTE_5[4] VPS_ PDC_UTC_ BYTE_6[4] VPS_ PDC_UTC_ BYTE_7[4] VPS_ PDC_UTC_ BYTE_8[4] VPS_ PDC_UTC_ BYTE_9[4] VPS_ PDC_UTC_ BYTE_10[4] VPS_ PDC_UTC_ BYTE_11[4] VPS_ PDC_UTC_ BYTE_12[4] VITC_ DATA_0[4] VITC_ DATA_1[4] VITC_ DATA_2[4] VITC_ DATA_3[4] VITC_ DATA_4[4] VITC_ DATA_5[4] VITC_ DATA_6[4] VITC_ DATA_7[4] VITC_ DATA_8[4] VITC_CRC[4] WSS_CGMS_ CB_CHANGE
3 GS_VPS_ PDC_UTC_ BYTE_3[3] VPS_ PDC_UTC_ BYTE_4[3] VPS_ PDC_UTC_ BYTE_5[3] VPS_ PDC_UTC_ BYTE_6[3] VPS_ PDC_UTC_ BYTE_7[3] VPS_ PDC_UTC_ BYTE_8[3] VPS_ PDC_UTC_ BYTE_9[3] VPS_ PDC_UTC_ BYTE_10[3] VPS_ PDC_UTC_ BYTE_11[3] VPS_ PDC_UTC_ BYTE_12[3] VITC_ DATA_0[3] VITC_ DATA_1[3] VITC_ DATA_2[3] VITC_ DATA_3[3] VITC_ DATA_4[3] VITC_ DATA_5[3] VITC_ DATA_6[3] VITC_ DATA_7[3] VITC_ DATA_8[3] VITC_CRC[3]
2 GS_VPS_ PDC_UTC_ BYTE_3[2] VPS_ PDC_UTC_ BYTE_4[2] VPS_ PDC_UTC_ BYTE_5[2] VPS_ PDC_UTC_ BYTE_6[2] VPS_ PDC_UTC_ BYTE_7[2] VPS_ PDC_UTC_ BYTE_8[2] VPS_ PDC_UTC_ BYTE_9[2] VPS_ PDC_UTC_ BYTE_10[2] VPS_ PDC_UTC_ BYTE_11[2] VPS_ PDC_UTC_ BYTE_12[2] VITC_ DATA_0[2] VITC_ DATA_1[2] VITC_ DATA_2[2] VITC_ DATA_3[2] VITC_ DATA_4[2] VITC_ DATA_5[2] VITC_ DATA_6[2] VITC_ DATA_7[2] VITC_ DATA_8[2] VITC_CRC[2]
1 GS_VPS_ PDC_UTC_ BYTE_3[1] VPS_ PDC_UTC_ BYTE_4[1] VPS_ PDC_UTC_ BYTE_5[1] VPS_ PDC_UTC_ BYTE_6[1] VPS_ PDC_UTC_ BYTE_7[1] VPS_ PDC_UTC_ BYTE_8[1] VPS_ PDC_UTC_ BYTE_9[1] VPS_ PDC_UTC_ BYTE_10[1] VPS_ PDC_UTC_ BYTE_11[1] VPS_ PDC_UTC_ BYTE_12[1] VITC_ DATA_0[1] VITC_ DATA_1[1] VITC_ DATA_2[1] VITC_ DATA_3[1] VITC_ DATA_4[1] VITC_ DATA_5[1] VITC_ DATA_6[1] VITC_DATA_ 7[1] VITC_ DATA_8[1] VITC_CRC[1]
0 GS_VPS_ PDC_UTC_ BYTE_3[0] VPS_ PDC_UTC_ BYTE_4[0] VPS_ PDC_UTC_ BYTE_5[0] VPS_ PDC_UTC_ BYTE_6[0] VPS_ PDC_UTC_ BYTE_7[0] VPS_ PDC_UTC_ BYTE_8[0] VPS_ PDC_UTC_ BYTE_9[0] VPS_ PDC_UTC_ BYTE_10[0] VPS_ PDC_UTC_ BYTE_11[0] VPS_ PDC_UTC_ BYTE_12[0] VITC_ DATA_0[0] VITC_ DATA_1[0] VITC_ DATA_2[0] VITC_ DATA_3[0] VITC_ DATA_4[0] VITC_ DATA_5[0] VITC_ DATA_6[0] VITC_ DATA_7[0] VITC_ DATA_8[0] VITC_CRC[0]
Value -
(Hex) -
136
88
R
-
-
137
89
R
-
-
138
8A
R
-
-
139
8B
R
-
-
140
8C
R
-
-
141
8D
R
-
-
142
8E
R
-
-
143
8F
R
-
-
144
90
R
-
-
146 147 148 149 150 151 152 153 154 155 156
92 93 94 95 96 97 98 99 9A 9B 9C
R R R R R R R R R R RW
- - - - - - - - - - 00110000
- - - - - - - - - - 30
1
To access the registers listed in Table 102, SUB_USR_EN in Register Address 0x0E must be programmed to 1.
Rev. A | Page 79 of 112
ADV7180
Table 103. Register Map Descriptions (Normal Operation)
Subaddress 0x00 Register Input Control Bit Description INSEL [3:0]. The INSEL bits allow the user to select an input channel and the input format. Refer to Table 9 and Table 8 for full routing details. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 VID_SEL [3:0]. The VID_SEL bits allow the user to select the input video standard. 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comments LQFP-64 LFCSP-40 Composite Composite Composite Reserved Composite Reserved Composite Composite Composite S-Video Composite Composite Reserved S-Video Notes
0
0
0
1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0x01 Video Selection Reserved. ENVSPROC. Reserved. BETACAM. ENHSPLL. Reserved. 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0
0 1 0 1
S-Video Reserved S-Video Reserved YPrPb YPrPb YPrPb Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Autodetect PAL B/G/H/I/D, NTSC (without pedestal), SECAM Autodetect PAL B/G/H/I/D, NTSC M (with pedestal), SECAM Autodetect PAL N, NTSC M (without pedestal), SECAM Autodetect PAL N, NTSC M (with pedestal), SECAM NTSC J NTSC M PAL 60 NTSC 4.43 PAL B/G/H/I/D PAL N (B/G/H/I/D without pedestal) PAL M (without pedestal) PAL M PAL Combination N PAL Combination N (with pedestal) SECAM SECAM (with pedestal) Set to default Disable vsync processor Enable vsync processor Set to default Standard video input Betacam input enable Disable hsync processor Enable hsync processor Set to default
Mandatory write required for Y/C (S-video mode) Reg 0x58 = 0x04; see Reg 0x58 for bit description
Rev. A | Page 80 of 112
ADV7180
Subaddress 0x03 Register Output Control Bit Description SD_DUP_AV. Duplicates the AV codes from the luma into the chroma path. Reserved. OF_SEL [3:0]. Allows the user to choose from a set of output formats. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TOD. Three-state output drivers. This bit allows the user to three-state the output drivers: P[19:0], HS, VS, FIELD, and SFL. VBI_EN. Allows VBI data (Lines 1 to 21) to be passed through with only a minimum amount of filtering performed. RANGE. Allows the user to select the range of output values. Can be ITU-R BT.656 compliant, or can fill the whole accessible number range. EN_SFL_PIN. 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comments LQFP-64 LFCSP-40 AV codes to suit 8-bit interleaved data output AV codes duplicated (for 16-bit interfaces) Set as default Reserved Reserved 16-bit @ LLC1 4:2:2 8-bit @ LLC1 4:2:2 ITU-R BT.656 Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Output pins enabled Drivers three-stated Notes
Options apply to ADV7180 LQFP-64 only
See also TIM_OE and TRI_LLC
0 1
All lines filtered and scaled Only active video region filtered
0x04
Extended Output Control
0 1
16 < Y < 235, 16 < C < 240 1 < Y < 254, 1 < C < 254
ITU-R BT.656 Extended range
0 1 0 1
BL_C_VBI. Blank chroma during VBI. If set, it enables data in the VBI region to be passed through the decoder undistorted. TIM_OE. Timing signals output enable. Reserved. Reserved. BT.656-4. Allows the user to select an output mode compatible with ITU-R BT.656-3/4. 0x05 0x06 Reserved Reserved x 1 0 1 x
SFL output is disabled SFL information output on the SFL pin Decode and output color Blank Cr and Cb
SFL output enables encoder and decoder to be connected directly During VBI
0 1
HS, VS, F three-stated HS, VS, F forced active
Controlled by TOD
ITU-R BT.656-3 compatible ITU-R BT.656-4 compatible
Rev. A | Page 81 of 112
ADV7180
Subaddress 0x07 Register Autodetect Enable Bit Description AD_PAL_EN. PAL B/G/I/H autodetect enable. AD_NTSC_EN. NTSC autodetect enable. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 1 0 1 AD_PALM_EN. PAL M autodetect enable. 0 1 AD_PALN_EN. PAL N autodetect enable. 0 1 AD_P60_EN. PAL 60 autodetect enable. 0 1 AD_N443_EN. NTSC 4.43 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. 0 1 AD_SEC525_EN. SECAM 525 autodetect enable. 0x08 Contrast Register CON[7:0]. Contrast adjust. This is the user control for contrast adjustment. Reserved. BRI[7:0]. This register controls the brightness of the video signal. HUE[7:0]. This register contains the value for the color hue adjustment. DEF_VAL_EN. Default value enable. 0 1 1 0 1 Comments LQFP-64 LFCSP-40 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Luma gain = 1 Notes
0
0
0
0
0
0
0
0x00 gain = 0, 0x80 gain = 1, 0xFF gain = 2
0x09 0x0A
Reserved Brightness Register
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0x0B
Hue Register
0
0
0
0
0
0
0
0
0x00 = 0IRE, 0x7F = +100IRE, 0x80 = -100IRE Hue range = -90 to +90
0x0C
Default Value Y
0 1
DEF_VAL_AUTO_EN. Default value.
0 1 0 0 1 1 0 1
Free-run mode dependent on DEF_VAL_AUTO_EN Force free-run mode on and output blue screen Disable free-run mode Enable automatic free-run mode (blue screen) Y[7:0] = {DEF_Y[5:0], 0, 0}
0x0D
Default Value C
0x0E
ADI Control
DEF_Y[5:0]. Default value Y. This register holds the Y default value. DEF_C[7:0]. Default value C. The Cr and Cb default values are defined in this register. Reserved. SUB_USR_EN. Enables user to access the interrupt/VDP register map. Reserved.
When lock is lost, free-run mode can be enabled to output stable timing, clock, and a set color Default Y value output in free-run mode
0
1
1
1
1
1
0
0
Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0} Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0}
Default Cb/Cr value output in free-run mode; default values give blue screen output See Figure 50
0 0 1 0 0
0
0
0
0
Set as default Access main register space Access interrupt/VDP register space Set as default
Rev. A | Page 82 of 112
ADV7180
Subaddress 0x0F Register Power Management Bit Description Reserved. PDBP. Power-down bit priority selects between PWRDWN bit or pin control. Reserved. PWRDWN. Powerdown places the decoder into a full power-down mode. Reserved. RESET. Chip reset, loads all I2C bits with default values. 0 0 1 0 0 1 0 Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 1 Comments LQFP-64 LFCSP-40 Set to default Chip power-down controlled by pin Bit has priority (pin disregarded) Set to default System functional Powered down Set to default Normal operation Start reset sequence Executing reset takes approx. 2 ms; this bit is self-clearing Provides information about the internal status of the decoder Notes
See PDBP, 0x0F Bit 2
0x10
Status Register 1 (Read Only)
IN_LOCK. LOST_LOCK. FSC_LOCK. FOLLOW_PW. AD_RESULT[2:0]. Autodetection result reports the standard of the input video. 0 0 0 0 1 1 1 1 x 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1
x x x x
0x11
IDENT (Read Only)
0x12
Status Register 2 (Read Only)
COL_KILL. IDENT[7:0]. Provides identification on the revision of the part. MVCS DET. MVCS T3. MV PS DET. MV AGC DET. LL NSTD. FSC NSTD. Reserved. INST_HLOCK. GEMD. SD_OP_50Hz. CVBS. FREE_RUN_ACT. STD FLD LEN. INTERLACED. PAL_SW_LOCK.
1 = in lock (now) 1 = lost lock (since last read) 1 = FSC lock (now) 1 = peak white AGC mode active NTSM M/J NTSC 4.43 PAL M PAL 60 PAL B/G/H/I/D SECAM PAL Combination N SECAM 525 1 = color kill is active
Detected standard
1
0
1
1
Color kill Power-up value = 0x1B
x x x x x x x x x x 0 1 0 1 x x x x 0 0 1 0 1 0
MV color striping detected MV color striping type MV pseudosync detected MV AGC pulses detected Nonstandard line length FSC frequency nonstandard 1 = horizontal lock achieved 1 = Gemstar data detected SD 60 Hz detected SD 50 Hz detected Y/C signal detected CVBS signal detected 1 = free-run mode active 1 = field length standard 1 = interlaced video detected 1 = swinging burst detected Set to default Current sources switched off Current sources enabled
1 = detected 0 = Type 2 1 = Type 3 1 = detected 1 = detected 1 = detected 1 = detected Unfiltered
0x13
Status Register 3 (Read Only)
SD field rate detect Result of CVBS and Y/C autodetection Blue screen output Correct field length found Field sequence found Reliable swinging burst sequence
0x14
Analog Clamp Control
Reserved. CCLEN. Current clamp enable allows the user to switch off the current sources in the analog front. Reserved.
0
0
0
Set to default
Rev. A | Page 83 of 112
ADV7180
Subaddress 0x15 Register Digital Clamp Control 1 Bit Description Reserved. Digital clamp freeze (DCFE) DCT[1:0]. Digital clamp timing determines the time constant of the digital fine clamp circuitry. Reserved. YSFM[4:0]. Selects Y shaping filter mode in CVBS-only mode. Allows the user to select a wide range of low-pass and notch filters. If either auto mode is selected, the decoder selects the optimum Y filter depending on the CVBS video source quality (good vs. bad). Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 x x x x 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 Comments LQFP-64 LFCSP-40 Set to default Digital clamp on Digital clamp off Slow (TC = 1 sec) Medium (TC = 0.5 sec) Fast (TC = 0.1 sec) TC dependent on video Set to default Auto wide notch for poor quality sources or wideband filter with comb for good quality input Auto narrow notch for poor quality sources or wideband filter with comb for good quality input SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR601) PAL NN1 PAL NN2 PAL NN3 PAL WN1 PAL WN2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Reserved Auto selection 15.0 MHz Auto selection 2.17 MHz SH1 SH2 SH3 SH4 SH5 Wideband mode Notes
0x17
Shaping Filter Control
Decoder selects optimum Y shaping filter depending on CVBS quality
0
0
0
0
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
If one of these modes is selected, the decoder does not change filter modes; depending on video quality, a fixed filter response (the one selected) is used for good and bad quality video
CSFM[2:0]. C shaping filter mode allows selection from a range of low-pass chrominance filters. If either auto mode is selected, the decoder selects the optimum C filter depending on the CVBS video source quality (good vs. bad). Nonauto settings force a C filter for all standards and quality of CVBS video.
Automatically selects a C filter based on video standard and quality Selects a C filter for all video standards and for good and bad video
Rev. A | Page 84 of 112
ADV7180
Subaddress 0x18 Register Shaping Filter Control 2 Bit Description WYSFM[4:0]. Wideband Y shaping filter mode allows the user to select which Y shaping filter is used for the Y component of Y/C, YPrPb, B/W input signals. It is also used when a good quality input CVBS signal is detected. For all other inputs, the Y shaping filter chosen is controlled by YSFM[4:0]. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 ~ ~ ~ ~ 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ~ 1 Comments LQFP-64 LFCSP-40 Reserved, do not use Reserved, do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Reserved, Do not use Reserved, Do not use Reserved, Do not use Notes
Reserved. WYSFMOVR. Enables the use of automatic WYSFM filter. 0x19 Comb Filter Control PSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (PAL). NSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (NTSC). Reserved. Reserved. EN28XTAL. TRI_LLC.
0 0 1
0
0 0 1 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 x x
0 1 0 1
0x1D
ADI Control 2
x
Set to default Autoselection of best filter Manual select filter using WYSFM[4:0] Narrow Medium Wide Widest Narrow Medium Medium Wide Set as default Set to default Use 27 MHz crystal Use 28 MHz crystal LLC pin active LLC pin three-stated
0 1 0 1
Rev. A | Page 85 of 112
ADV7180
Subaddress 0x27 Register Pixel Delay Control Bit Description LTA[1:0]. Luma timing adjust allows the user to specify a timing difference between chroma and luma samples. Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 1 1 1 0 0 0 0 0 0 1 Comments LQFP-64 LFCSP-40 No delay Luma 1 clock (37 ns) late Luma 2 clock (74 ns) early Luma 1 clock (37 ns) early Set to 0 Not valid setting Notes CVBS mode LTA[1:0] = 00b, S-video mode LTA[1:0] = 01b, YPrPb mode LTA[1:0] = 01b
CVBS mode CTA[2:0] = 011b, S-Video mode CTA[2:0] = 101b, YPrPb mode CTA[2:0] = 110b
0 0 0 1 1 1 1 AUTO_PDC_EN. Automatically programs the LTA/CTA values so that luma and chroma are aligned at the output for all modes of operation. SWPC. Allows the Cr and Cb samples to be swapped. 0x2B Misc Gain Control PW_UPD. Peak white update determines the rate of gain. Reserved. CKE. Color kill enable allows the color kill function to be switched on and off. Reserved. CAGC[1:0]. Chroma automatic gain control selects the basic mode of operation for the AGC in the chroma path. Reserved. LAGC[2:0]. Luma automatic gain control selects the mode of operation for the gain control in the luma path. 1 0 1 1 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
Chroma + 2 pixels (early) Chroma + 1 pixel (early) No delay Chroma - 1 pixel (late) Chroma - 2 pixels (late) Chroma - 3 pixels (late) Not valid setting Use values in LTA[1:0] and CTA[2:0] for delaying luma/chroma LTA and CTA values determined automatically
1
0 1 0 1 0 0 0 0
No swapping Swap the Cr and Cb O/P samples Update once per video line Update once per field Set to default Color kill disabled Color kill enabled Set to default Manual fixed gain Use luma gain for chroma Automatic gain Freeze chroma gain Set to 1 Manual fixed gain Reserved Peak white algorithm on Reserved Peak white algorithm off Reserved Reserved Freeze gain Set to 1
See Swap_CR_CB_WB, Addr 0x89
Peak white must be enabled; see LAGC[2:0]
For SECAM color kill, threshold is set at 8%; see CKILLTHR[2:0]
0x2C
AGC Mode Control
0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1
0 1 0 1
Use CMG[11:0] Based on color burst
Use LMG[11:0] Blank level to sync tip Blank level to sync tip
Reserved.
Rev. A | Page 86 of 112
ADV7180
Subaddress 0x2D Register Chroma Gain Control 1 Bit Description CMG[11:8]/CG[11:8]. In manual mode, the chroma gain control can be used to program a desired manual chroma gain. In auto mode, it can be used to read back the current gain value. Reserved. CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. CMG[7:0]/CG[7:0]. Chroma manual gain lower eight bits. See CMG[11:8]/CG[11:8] for description. LMG[11:8]/LG[11:8]. In manual mode, luma gain control can be used to program a desired manual chroma gain. In auto mode, it can be used to read back the actual gain value used. Reserved. LAGT[1:0]. Luma automatic gain timing allows adjustment of the luma AGC tracking speed. LMG[7:0]/LG[7:0]. Luma manual gain lower eight bits. See LMG[11:8]/ LG[11:8] for description. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 1 0 0 Comments LQFP-64 LFCSP-40 Notes CAGC[1:0] settings decide in which mode CMG[11:0] operates
1 0 0 1 1 0 0 1 0 1 0 0
1
Set to 1 Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive 0 0 0 0 CMG[11:0] = 750d; gain is 1 in NTSC. CMG[11:0] = 741d; gain is 1 in PAL
Has an effect only if CAGC[1:0] is set to autogain (10)
0x2E
Chroma Gain Control 2
0
Min value is 0 dec (G = 1/1000) Max value is 3750 dec (Gain = 5)
0x2F
Luma Gain Control 1
x
x
x
x
LAGC[1:0] settings decide in which mode LMG[11:0] operates
1 0 0 1 1 x 0 1 0 1 x x
1
Set to 1 Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Adaptive x x x x LMG[11:0] = 1600d; gain is 1 in NTSC LMG[11:0] = 1630d; gain is 1 in PAL
Only has an effect if LAGC[1:0] is set to auto gain (001, 010, 011,or 100)
0x30
Luma Gain Control 2
x
Minimum value NTSC 2048 (G = 0.5) PAL 2048 (G = 0.5) Maximum value NTSC 4095 (G = 2) PAL 4095 (G = 2) HSE = Hsync end HSB = Hsync begin
0x31
VS/FIELD Control 1
Reserved. HVSTIM. Selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode.
0 0 1 0
1
0
Set to default Start of line relative to HSE Start of line relative to HSB EAV/SAV codes generated to suit Analog Devices encoders Manual VS/FIELD position controlled by the 0x32, 0x33, and 0xE5 to 0xEA registers Set to default Set to default VS goes high in the middle of the line (even field) VS changes state at the start of the line (even field) VS goes high in the middle of the line (odd field) VS changes state at the start of the line (odd field) Set to default VS goes low in the middle of the line (even field) VS changes state at the start of the line (even field) VS goes low in the middle of the line (odd field) VS changes state at the start of the line odd field
1
0x32
VS/FIELD Control 2
Reserved. Reserved. VSBHE.
0
0 0 1
0 0
0
0
0
0
1
NEWAVMODE bit must be set high
VSBHO.
0 1
0x33
VS/FIELD Control 3
Reserved. VSEHE.
0 0 1
0
0
1
0
0
NEWAVMODE bit must be set high
VSEHO.
0 1 Rev. A | Page 87 of 112
ADV7180
Subaddress 0x34 Register HS Position Control 1 Bit Description HSE[10:8]. HS end allows positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows positioning of the HS output within the video line. Reserved. HSB[7:0] See above, using HSB[10:0] and HSE[10:0], users can program the position and length of HS output signal. HSE[7:0] See above. PCLK. Sets polarity of LLC1. Reserved. PF. Sets the FIELD polarity. Reserved. PVS. Sets the VS polarity. Reserved. PHS. Sets HS polarity. 0x38 NTSC Comb Control YCMN[2:0]. Luma comb mode, NTSC. 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 Comments LQFP-64 LFCSP-40 HS output ends HSE[10:0] pixels after the falling edge of hsync Notes Using HSB and HSE the user can program the position and length of the output hsync
0 0 0 0
Set to 0 HS output starts HSB[10:0] pixels after the falling edge of hsync Set to 0
0x35
HS Position Control 2
0 0
0
0
0
0
0
1
0
0x36 0x37
HS Position Control 3 Polarity
0
0
0
0
0
0
0
0 0 1
0 0 1
0
CCMN[2:0]. Chroma comb mode, NTSC.
1 1
0 0
0 1
1
1
0
1
1
1
CTAPSN[1:0]. Chroma comb taps, NTSC.
0 0 1 1
0 1 0 1 Rev. A | Page 88 of 112
Invert polarity Normal polarity as per the timing diagrams Set to 0 Active high Active low Set to 0 Active high Active low Set to 0 Active high Active low Adaptive 3-line, 3-tap luma Use low-pass notch Fixed luma comb (2-line) Fixed luma comb (3-line) Fixed luma comb (2-line) 3-line adaptive for CTAPSN = 01 4-line adaptive for CTAPSN = 10 5-line adaptive for CTAPSN = 11 Disable chroma comb Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Fixed 3-line for CTAPSN = 01 Fixed 4-line for CTAPSN = 10 Fixed 5-line for CTAPSN = 11 Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Adapts three to two lines Not used Adapts five to three lines Adapts five to four lines
Top lines of memory All lines of memory Bottom lines of memory
Top lines of memory
All lines of memory
Bottom lines of memory
ADV7180
Subaddress 0x39 Register PAL Comb Control Bit Description YCMP[2:0]. Luma comb mode, PAL. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 CCMP[2:0]. Chroma comb mode, PAL. 0 0 0 0 1 1 1 0 0 0 1 Comments LQFP-64 LFCSP-40 Adaptive 5-line, 3-tap luma comb Use low-pass notch Fixed luma comb Fixed luma comb (5-line) Fixed luma comb (3-line) 3-line adaptive for CTAPSN = 01 4-line adaptive for CTAPSN = 10 5-line adaptive for CTAPSN = 11 Disable chroma comb Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Fixed 3-line for CTAPSN = 01 Fixed 4-line for CTAPSN = 10 Fixed 5-line for CTAPSN = 11 Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Adapts five to two lines (two taps) Not used Adapts five to three lines (three taps) Adapts five to four lines (four taps) Notes
Top lines of memory All lines of memory Bottom lines of memory
1 1
0 0
0 1
Top lines of memory
1
1
0
All lines of memory
1
1
1
Bottom lines of memory
CTAPSP[1:0]. Chroma comb taps, PAL.
0 0 1 1
0 1 0 1 0
0x3A
ADC Control
MUX PDN override. MUX power-down override. When INSEL[3:0] is used, unused channels are automatically powered down. PWRDWN_MUX_2. Enables power-down of MUX_2 and associated channel clamp and buffer.
1
No control over powerdown for muxes and associated channel circuit Allows power-down of MUX_0/1/2 and associated channel circuit MUX_2 and associated channel in normal operation
0
1 PWRDWN_MUX_1. Enables power-down of MUX_1 and associated channel clamp and buffer. 0
Power down MUX_2 and associated channel operation MUX_1 and associated channel in normal operation
MUX PDN override =1
1 PWRDWN_MUX_0. Enables power-down of MUX_0 and associated channel clamp and buffer. 0
Power down MUX_1 and associated channel operation MUX_0 and associated channel in normal operation
MUX PDN override =1
1 Reserved. 0 0 0 1
Power down MUX_0 and associated channel operation Set as default
MUX PDN override =1
Rev. A | Page 89 of 112
ADV7180
Subaddress 0x3D Register Manual Window Control Bit Description Reserved. CKILLTHR[2:0]. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 1 0 Comments LQFP-64 LFCSP-40 Set to default Kill at 0.5% Kill at 1.5% Kill at 2.5% Kill at 4% Kill at 8.5% Kill at 16% Kill at 32% Reserved Set to default Set to default SFL compatible with ADV7190/ADV7191/ ADV7194 encoders SFL compatible with ADV717x/ADV7173x encoders Set to default GDECEL[15:0]: sixteen individual enable bits that select the lines of video (even field Line 10 to Line 25) that the decoder checks for Gemstar-compatible data GDECOL[15:0]: sixteen individual enable bits that select the lines of video (odd field Line 10 to Line 25) that the decoder checks for Gemstar-compatible data Split data into half-byte Notes CKE = 1 enables the color kill function and must be enabled for CKILLTHR[2:0] to take effect
0x41
Resample Control
Reserved. Reserved. SFL_INV. Controls the behavior of the PAL switch bit.
1
0x48 0x49
Gemstar Control 1 Gemstar Control 2
Reserved. GDECEL[15:8]. See the Comments column. GDECEL[7:0].
0 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0x4A 0x4B
Gemstar Control 3 Gemstar Control 4
GDECOL[15:8]. See the Comments column. GDECOL[7:0].
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0x4C
Gemstar Control 5
GDECAD. Controls the manner in which decoded Gemstar data is inserted into the horizontal blanking period. Reserved. CTI_EN. CTI enable. CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry. x x x x x x x
0
LSB = Line 10 MSB = Line 25 Default = Do not check for Gemstar-compatible data on any lines [10 to 25] in even fields LSB = Line 10 MSB = Line 25 Default = Do not check for Gemstar-compatible data on any lines [10 to 25] in odd fields To avoid 00/FF code
1
0x4D
CTI DNR Control 1
0 1 0 1
Output in straight 8-bit format Undefined Disable CTI Enable CTI Disable CTI alpha blender Enable CTI alpha blender
0 0 1 1 0 0 1 1 0 1 0 0 0 1
0 1 0 1
Reserved. DNR_EN. Enable or bypass the DNR block. 0x4E CTI DNR Control 2 Reserved. CTI_C_TH[7:0]. Specifies how big the amplitude step must be to be steepened by the CTI block. DNR_TH[7:0]. Specifies the maximum edge that is interpreted as noise and is therefore blanked.
0
0
0
Sharpest mixing Sharp mixing Smooth Smoothest Set to default Bypass the DNR block Enable the DNR block Set to default Set to 0x04 for AV input; set to 0x0A for tuner input
0x50
CTI DNR Control 4
0
0
0
0
1
0
0
0
Rev. A | Page 90 of 112
ADV7180
Subaddress 0x51 Register Lock Count Bit Description CIL[2:0]. Count into lock determines the number of lines the system must remain in lock before showing a locked status. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Comments LQFP-64 LFCSP-40 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100,000 lines of video 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100,000 lines of video Over field with vertical info Line-to-line evaluation Lock status set only by horizontal lock Lock status set by horizontal lock and subcarrier lock FIELD VSYNC Set to default CVBS/YPrPb modes only Y/C mode only Set to default Outputs 0 to GPO0, Pin 13 Outputs 1 to GPO0, Pin 13 Outputs 0 to GPO1, Pin 12 Outputs 1 to GPO1, Pin 12 Outputs 0 to GPO2, Pin 56 Outputs 1 to GPO2, Pin 56 Outputs 0 to GPO3, Pin 55 Outputs 1 to GPO3, Pin 55 GPO[3:0] three-stated GPO[3:0] enabled Set to default LLC1 (nominal 27 MHz) selected out on LLC1 pin LLC2 (nominal 13.5 MHz) selected out on LLC1 pin Set to default CCAP1[7] contains parity bit for Byte 0 CCAP2[7] contains parity bit for Byte 0 Mandatory write GPO_Enable must be set to 1 for these bits to take effect Notes
COL[2:0]. Count out of lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status.
SRLS. Select raw lock signal. Selects the determination of the lock status. FSCLE. FSC lock enable.
0x58
VSYNC/FIELD Pin Control
VS/FIELD. Vsync or field output. ADV7180 LFCSP-40 only. Reserved. ADC Sampling Control.
0 1 0 0 1
Pin 37 on LFCSP-40
0x59
General-Purpose Outputs
Reserved. GPO[3:0]. ADV7180 LQFP-64 only.
0
0
0
0
0 0 1 0 1 0 1 0 1
GPO_Enable. Reserved. Reserved. LLC_PAD_SEL[2:0]. Enables manual selection of clock for LLC1 pin. Reserved. CCAP1[7:0] Closed caption data register. CCAP2[7:0] Closed caption data register. 0 0 0 1 0 x x 0
0 1 0 0 0 0 1 0 0 0
0x8F
Free-Run Line Length 1
For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010
0x99 0x9A
CCAP1 (Read Only) CCAP2 (Read Only)
x x
x x
x x
x x
x x
x x
x x
Rev. A | Page 91 of 112
ADV7180
Subaddress 0x9B Register Letterbox 1 (Read Only) Letterbox 2 (Read Only) Bit Description LB_LCT[7:0]. Letterbox data register. LB_LCM[7:0]. Letterbox data register. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 x x x x x x x x Comments LQFP-64 LFCSP-40 Reports the number of black lines detected at the top of active video Reports the number of black lines detected in the bottom half of active video if subtitles are detected Reports the number of black lines detected at the bottom of active video Set as default Turn off CRC check CGMSD goes high with valid checksum Set as default No connect AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No connect No connect No connect No connect AIN3 AIN4 AIN5 AIN6 No connect 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 Disable Enable Default threshold for the detection of black lines This bit must be set to 1 for manual muxing 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 No connect No connect AIN2 No connect No connect AIN5 AIN6 No connect Notes This feature examines the active video at the start and end of each field; it enables format detection even if the video is not accompanied by a CGMS or WSS sequence
0x9C
x
x
x
x
x
x
x
x
0x9D
Letterbox 3 (Read Only) CRC Enable (Write Only)
LB_LCB[7:0]. Letterbox data register. Reserved. CRC_ENABLE. Enable CRC checksum decoded from CGMS packet to validate CGMSD. Reserved. MUX_0[3:0]. Manual muxing control for MUX0. This setting controls which input is routed to the ADC for processing.
x
x
x
x
x
x
x
x
0xB2
0 0 1
0
0
0
0
1
1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0xC3
ADC SWITCH 1
No connect AIN1 No connect No connect AIN2 AIN3 No connect No connect No connect No connect No connect No connect AIN2 AIN3 No connect No connect No connect No connect No connect No connect No connect AIN3 No connect No connect
MAN_MUX_EN = 1
Reserved. MUX_1[3:0]. Manual muxing control for MUX1. This setting controls which input is routed to the ADC for processing.
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
MAN_MUX_EN = 1
0xC4
ADC Switch 2
Reserved. MUX_2[3:0]. Manual muxing control for MUX2. This setting controls which input is routed to the ADC for processing.
MAN_MUX_EN = 1
0xDC
Letterbox Control 1
0xDD
Letterbox Control 2
Reserved. MAN_MUX_EN. Enable manual setting of the input signal muxing. LB_TH [4:0]. Sets the threshold value that determines if a line is black. Reserved. LB_EL[3:0]. Programs the end line of the activity window for LB detection (end of field). LB_SL[3:0]. Program the start line of the activity window for LB detection (start of field).
1
0
1 1 1 0 0
Set as default LB detection ends with the last line of active video on a field, 1100b: 262/525 Letterbox detection aligned with the start of active video, 0100b: 23/286 NTSC
0
1
0
0
Rev. A | Page 92 of 112
ADV7180
Subaddress 0xDE Register ST_Noise Readback 1 (Read Only) Bit Description ST NOISE[10:0]. Noise measurement. ST_NOISE[10:8]. ST_Noise_Valid. ST_NOISE[7:0]. Reserved. SD_OFF_CB [7:0]. Adjusts the hue by selecting the offset for the Cb channel. SD_OFF_CR [7:0]. Adjusts the hue by selecting the offset for the Cr channel. SD_SAT_CB [7:0]. Adjusts the saturation by affecting gain on the Cb channel. SD_SAT_CR [7:0]. Adjusts the saturation by affecting gain on the Cr channel. NVBEG[4:0]. Number of lines after lCOUNT rollover to set V high. NVBEGSIGN. x 0 1 x 0 0 x 0 0 x 1 0 Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 Comments LQFP-64 LFCSP-40 Notes
x x x 0 0 x 1 0
x
x When = 1, ST_Noise[10:0] is valid
0xDF 0xE0 0xE1
ST_Noise Readback 2 (Read Only) SD Offset Cb
x 0 0
x 0 0
0xE2
SD Offset Cr
1
0
0
0
0
0
0
0
0xE3
SD Saturation Cb
1
0
0
0
0
0
0
0
Chroma gain = 0 dB
0xE4
SD Saturation Cr
1
0
0
0
0
0
0
0
Chroma gain = 0 dB
0xE5
NTSC V Bit Begin
0
0
1
0
1
NTSC default (ITU-R BT.656)
0 1
0xE6
NTSC V Bit End
NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). NVBEGDELO. Delay V bit going high by one line relative to NVBEG (odd field). NVEND[4:0]. Number of lines after lCOUNT rollover to set V low. NVENDSIGN.
0 1 0 1 0 0 1 0 0
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line NTSC default (ITU-R BT.656)
0 1
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line
NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field).
0 1 0 1
Rev. A | Page 93 of 112
ADV7180
Subaddress 0xE7 Register NTSC F Bit Toggle Bit Description NFTOG[4:0]. Number of lines after lCOUNT rollover to toggle F signal. NFTOGSIGN. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 1 1 Comments LQFP-64 LFCSP-40 NTSC default Notes
0 1
0xE8
PAL V Bit Begin
NFTOGDELE. Delay F transition by one line relative to NFTOG (even field). NFTOGDELO. Delay F transition by one line relative to NFTOG (odd field). PVBEG[4:0]. Number of lines after lCOUNT rollover to set V high. PVBEGSIGN.
0 1 0 1 0 0 1 0 1
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line PAL default (ITU-R BT.656)
0 1
0xE9
PAL V Bit End
PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even field). PVBEGDELO. Delay V bit going high by one line relative to PVBEG (odd field). PVEND[4:0]. Number of lines after lCOUNT rollover to set V low. PVENDSIGN.
0 1 0 1 1 0 1 0 0
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line PAL default (ITU-R BT.656)
0 1
0xEA
PAL F Bit Toggle
PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V bit going low by one line relative to PVEND (odd field). PFTOG[4:0]. Number of lines after lCOUNT rollover to toggle F signal. PFTOGSIGN.
0 1 0 1 0 0 0 1 1
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line PAL default (ITU-R BT.656)
0 1
PFTOGDELE. Delay F transition by one line relative to PFTOG (even field). PFTOGDELO. Delay F transition by one line relative to PFTOG (odd field).
0 1 0 1
Set to low when manual programming Not suitable for user programming No delay Additional delay by one line No delay Additional delay by one line
Rev. A | Page 94 of 112
ADV7180
Subaddress 0xEB Register V Blank Control 1 Bit Description PVBIELCM[1:0]. PAL VBI even field line control. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 0 0 1 1 PVBIOLCM[1:0]. PAL VBI odd field line control. 0 0 1 1 NVBIELCM[1:0]. NTSC VBI even field line control. 0 0 1 1 PVBIOLCM[1:0]. NTSC VBI odd field line control. 0 0 1 1 0xEC V Blank Control 2 PVBIECCM[1:0]. PAL VBI even field color control. 0 1 0 1 0 0 1 1 PVBIOCCM[1:0]. PAL VBI odd field color control. 0 0 1 1 NVBIECCM[1:0]. NTSC VBI even field color control. 0 0 1 1 NVBIOCCM[1:0]. NTSC VBI 0 odd field color control. 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 Comments LQFP-64 LFCSP-40 VBI ends one line earlier (Line 335) ITU-R BT.470 compliant (Line 336) VBI ends one line later (Line 337) VBI ends two lines later (Line 338) VBI ends one line earlier (Line 22) ITU-R BT.470 compliant (Line 23) VBI ends one line later (Line 24) VBI ends two lines later (Line 25) VBI ends one line earlier (Line 282) ITU-R BT.470-compliant (Line 283) VBI ends one line later (Line 284) VBI ends two lines later (Line 285) VBI ends one line earlier (Line 20) ITU-R BT.470-compliant (Line 21) VBI ends one line later (Line 22) VBI ends two lines later (Line 23) Color output beginning Line 335 ITU-R BT.470-compliant color output beginning Line 336 Color output beginning Line 337 Color output beginning Line 338 Color output beginning Line 22 ITU-R BT.470-compliant color output beginning Line 23 Color output beginning Line 24 Color output beginning Line 25 Color output beginning Line 282 ITU-R BT.470-compliant color output beginning Line 283 VBI ends one line later (Line 284) Color output beginning Line 285 Color output beginning Line 20 ITU-R BT.470 compliant color output beginning Line 21 Color output beginning Line 22 Color output beginning Line 23 Notes Controls position of first active (comb filtered) line after VBI on even field in PAL
Controls position of first active (comb filtered) line after VBI on odd field in PAL
Controls position of first active (comb filtered) line after VBI on even field in NTSC
Controls position of first active (comb filtered) line after VBI on odd field in NTSC
Controls the position of first line that outputs color after VBI on even field in PAL
Controls the position of first line that outputs color after VBI on odd field in PAL
Controls the position of first line that outputs color after VBI on even field in NTSC
Controls the position of first line which outputs color after VBI on odd field in NTSC
1 1
0 1
Rev. A | Page 95 of 112
ADV7180
Subaddress 0xF3 Register AFE Control 1 Bit Description AA_FILT_EN[2:0]. Antialiasing filter enable. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 Comments LQFP-64 LFCSP-40 Antialiasing Filter 1 disabled Notes AA_FILT_MAN_OVR must be enabled to change settings defined by INSEL[3:0]
1 0 1 0 1 AA_FILT_MAN_OVR. Antialiasing filter override. Reserved. 0xF4 Drive Strength DR_STR_S[1:0]. Selects the drive strength for the sync output signals. 0 0 0 0 0 0 1 1 DR_STR_C[1:0]. Selects the drive strength for the clock output signal. 0 0 1 1 DR_STR[1:0]. Selects the drive strength for the data output signals. Can be increased or decreased for EMC or crosstalk reasons. Reserved. IFFILTSEL[2:0]. IF filter selection for PAL and NTSC. x x 0 0 0 0 1 1 1 1 Reserved. 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0xF8 IF Comp Control 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Antialiasing Filter 1 enabled Antialiasing Filter 2 disabled Antialiasing Filter 2 enabled Antialiasing Filter 3 disabled Antialiasing Filter 3 enabled Override disabled Override enabled
Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) Low drive strength (1x) Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) Bypass mode 2 MHz -3 dB -6 dB -10 dB Reserved 3 MHz -2 dB -5 dB -7 dB 0 dB NTSC filters
5 MHz -2 dB +3.5 dB +5 dB 6 MHz +2 dB +3 dB +5 dB
PAL filters
Rev. A | Page 96 of 112
ADV7180
Subaddress 0xF9 Register VS Mode Control Bit Description EXTEND_VS_MAX_FREQ. Bits (Shading Indicates Default State) 7 6 5 4 3 2 1 0 0 Comments LQFP-64 LFCSP-40 Limits maximum vsync frequency to 66.25 Hz (475 lines/frame) Limits maximum vsync frequency to 70.09 Hz (449 lines/frame) Limits minimum vsync frequency to 42.75 Hz (731 lines/frame) Limits minimum vsync frequency to 39.51 Hz (791 lines/frame) Autocoast mode 50 Hz coast mode 60 Hz coast mode Reserved Increases/decreases the gain for high frequency portions of the video signal. Specifies the maximum edge that is interpreted as noise and therefore blanked. Notes
1
EXTEND_VS_MIN_FREQ.
0
1
VS_COAST_MODE[1:0].
0 0 1 1 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0
This value sets up the output coast frequency
0xFB
Peaking Control
Reserved. PEAKING_GAIN[7:0].
0xFC
Coring Threshold 2
DNR_TH2[7:0].
0
0
0
0
0
1
0
0
Rev. A | Page 97 of 112
ADV7180
Table 104. Register Map Descriptions (Interrupt Operation)
Bit (Shading Indicates User Sub Map Address Register 0x40 Interrupt Configuration 1
Default State)
Bit Description INTRQ_OP_SEL[1:0]. Interrupt drive level select. 7654321 0 0 1 1 0 1 x 00 01 10 11 00 01 10 11 0 0 1 0 1 Comments Open drain Drive low when active Drive high when active Reserved Manual interrupt mode disabled Manual interrupt mode enabled Not used Reserved Pseudo sync only Color stripe only Pseudo sync or color stripe 3 XTAL periods 15 XTAL periods 63 XTAL periods Active until cleared No change SD input has caused the decoder to go from an unlocked state to a locked state No change SD input has caused the decoder to go from a locked state to an unlocked state Notes
MPU_STIM_INTRQ. Manual interrupt set mode. Reserved MV_INTRQ_SEL[1:0]. Macrovision interrupt select.
INTRQ_DUR_SEL[1:0]. Interrupt duration select.
0x42
Interrupt Status 1 (Read Only)
SD_LOCK_Q.
0 1 0 1 x x x 0 1 0 1
SD_UNLOCK_Q.
These bits can be cleared or masked in Registers 0x43 and 0x44, respectively
Reserved. Reserved. Reserved. SD_FR_CHNG_Q. MV_PS_CS_Q.
No Change Denotes a change in the free-run status No Change Pseudo sync/color striping detected. See Reg. 0x40 MV_INTRQ_SEL[1:0] for selection 0 1 0 1 0 0 0 Do not clear Clears SD_LOCK_Q bit Do not clear Clears SD_UNLOCK_Q bit Not used Not used Not used Do not clear Clears SD_FR_CHNG_Q bit Do not clear Clears MV_PS_CS_Q bit Not used Masks SD_LOCK_Q bit Unmasks SD_LOCK_Q bit Masks SD_UNLOCK_Q bit Unmasks SD_UNLOCK_Q bit Not used Not used Not used Masks SD_FR_CHNG_Q bit Unmasks SD_FR_CHNG_Q bit Masks MV_PS_CS_Q bit Unmasks MV_PS_CS_Q bit Not used
0x43
Interrupt Clear 1 (Write Only)
Reserved. SD_LOCK_CLR. SD_UNLOCK_CLR. Reserved. Reserved. Reserved. SD_FR_CHNG_CLR. MV_PS_CS_CLR. Reserved. SD_LOCK_MSK. SD_UNLOCK_MSK. Reserved. Reserved. Reserved. SD_FR_CHNG_MSK. MV_PS_CS_MSK. Reserved.
x
0 1 0 1 x 0 1 0 1 0 0 0 0 1 0 1 x
0x44
Interrupt Mask 1 (Read/Write)
Rev. A | Page 98 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x45 Raw Status 2 (Read Only)
Default State)
Bit Description CCAPD. 76543210 0 1 Reserved. EVEN_FIELD. Reserved. MPU_STIM_INTRQ. xx 0 1 0 1 GEMD_Q. 0 1 Reserved. SD_FIELD_CHNGD_Q. xx 0 1 Reserved. Reserved. MPU_STIM_INTRQ_Q. x x 0 1 0 1 0 1 00 0 1 x x 0 1 0 1 0 1 00 0 1 00 0 1 0 1 0 1 0 1 x 0 1 x x x Do not clear Clears SD_FIELD_CHNGD_Q bit Not used Not used Do not clear Clears MPU_STIM_INTRQ_Q bit Masks CCAPD_Q bit--VBI System 2 Unmasks CCAPD_Q bit-- VBI System 2 Masks GEMD_Q bit--VBI System 2 Unmasks GEMD_Q bit--VBI System 2 Not used Masks SD_FIELD_CHNGD_Q bit Unmasks SD_FIELD_CHNGD_Q bit Not used Masks MPU_STIM_INTRQ_Q bit Unmasks MPU_STIM_INTRQ_Q bit SD 60 Hz signal output SD 50 Hz signal output SD vertical sync lock not established SD vertical sync lock established SD horizontal sync lock not established SD horizontal sync lock established Not used SECAM lock not established SECAM lock established Not used Not used Not used SD signal has not changed field from odd to even or vice versa SD signal has changed Field from odd to even or vice versa Not used Not used Manual interrupt not set Manual interrupt set Do not clear--VBI System 2 Clears CCAPD_Q bit - VBI System 2 Do not clear Clears GEMD_Q bit MPU_STIM_INT = 0 MPU_STIM_INT = 1 Closed captioning not detected in the input video signal--VBI System 2 Closed captioning data detected in the video input signal--VBI System 2 Gemstar data not detected in the input video signal--VBI System 2 Gemstar data detected in the input video signal--VBI System 2 xxx 0 1 Current SD field is odd numbered Current SD field is even numbered Comments No CCAPD data detected-- VBI System 2 CCAPD data detected--VBI System 2 Notes These bits are status bits only; they cannot be cleared or masked; Register 0x46 is used for this purpose
0x46
Interrupt Status 2 (Read Only)
CCAPD_Q.
These bits can be cleared or masked by Registers 0x47 and 0x48, respectively Note that interrupt in Register 0x46 for the CCAP, Gemstar, CGMS, and WSS data is using the Mode 1 data slicer
0x47
Interrupt Clear 2 (Write Only)
CCAPD_CLR. GEMD_CLR. Reserved. SD_FIELD_CHNGD_CLR. Reserved. Reserved. MPU_STIM_INTRQ_CLR.
Note that interrupt in Register 0x46 for the CCAP, Gemstar, CGMS, and WSS data is using the Mode 1 data slicer
0x48
Interrupt Mask 2 (Read/Write)
CCAPD_MSK.
GEMD_MSK. Reserved. SD_FIELD_CHNGD_MSK. Reserved. MPU_STIM_INTRQ_MSK. 0x49 Raw Status 3 (Read Only) SD_OP_50Hz. SD 60 Hz/50 Hz frame rate at output. SD_V_LOCK. SD_H_LOCK. Reserved. SCM_LOCK. Reserved. Reserved. Reserved.
Note that interrupt in Register 0x46 for the CCAP, Gemstar, CGMS, and WSS data is using the Mode 1 data slicer.
These bits are status bits only; they cannot be cleared or masked; Register 0x4A is used for this purpose
Rev. A | Page 99 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x4A Interrupt Status 3 (Read Only)
Default State)
Bit Description SD_OP_CHNG_Q. SD 60 Hz/50 Hz frame rate at output. 76543210 0 1 SD_V_LOCK_CHNG_Q. SD_H_LOCK_CHNG_Q. SD_AD_CHNG_Q. SD autodetect changed. 0 1 SCM_LOCK_CHNG_Q. SECAM lock. PAL_SW_LK_CHNG_Q. 0 1 Reserved. Reserved. SD_OP_CHNG_CLR. SD_V_LOCK_CHNG_CLR. SD_H_LOCK_CHNG_CLR. SD_AD_CHNG_CLR. SCM_LOCK_CHNG_CLR. PAL_SW_LK_CHNG_CLR. Reserved. Reserved. SD_OP_CHNG_MSK. SD_V_LOCK_CHNG_ MSK. SD_H_LOCK_CHNG_ MSK. SD_AD_CHNG_ MSK. SCM_LOCK_CHNG_ MSK. PAL_SW_LK_CHNG_ MSK. Reserved. Reserved. x x 0 1 0 1 0 1 0 1 x x 0 1 0 1 0 1 0 1 0 1 0 1 x x 0 1 0 1 0 1 0 1 0 1 Comments No change in SD signal standard detected at the output A change in SD signal standard is detected at the output No change in SD vsync lock status SD vsync lock status has changed No change in SD hsync lock status SD hsync lock status has changed No change in AD_RESULT[2:0] bits in Status Register 1 AD_RESULT[2:0] bits in Status Register 1 have changed No change in SECAM lock status SECAM lock status has changed No change in PAL swinging burst lock status PAL swinging burst lock status has changed Not used Not used Do not clear Clears SD_OP_CHNG_Q bit Do not clear Clears SD_V_LOCK_CHNG_Q bit Do not clear Clears SD_H_LOCK_CHNG_Q bit Do not clear Clears SD_AD_CHNG_Q bit Do not clear Clears SCM_LOCK_CHNG_Q bit Do not clear Clears PAL_SW_LK_CHNG_Q bit Not used Not used Masks SD_OP_CHNG_Q bit Unmasks SD_OP_CHNG_Q bit Masks SD_V_LOCK_CHNG_Q bit Unmasks SD_V_LOCK_CHNG_Q bit Masks SD_H_LOCK_CHNG_Q bit Unmasks SD_H_LOCK_CHNG_Q bit Masks SD_AD_CHNG_Q bit Unmasks SD_AD_CHNG_Q bit Masks SCM_LOCK_CHNG_Q bit Unmasks SCM_LOCK_CHNG_Q bit Masks PAL_SW_LK_CHNG_Q bit Unmasks PAL_SW_LK_CHNG_Q bit Not used Not used Notes These bits can be cleared and masked by Registers 0x4B and 0x4C, respectively
0x4B
Interrupt Clear 3 (Write only)
0x4C
Interrupt Mask 3 (Read/Write)
Rev. A | Page 100 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x4E Interrupt Status 4 (R d l )
Default State)
Bit Description VDP_CCAPD_Q. Reserved. VDP_CGMS_WSS_CHNGD_Q. See 0x9C Bit 4 of user sub map to determine whether interrupt is issued for a change in detected data or for when data is detected regardless of content. Reserved. VDP_GS_VPS_PDC_UTC_CHNG_Q. See 0x9C Bit 5 of User Sub Map to determine whether interrupt is issued for a change in detected data or for when data is detected regardless of content. Reserved. VDP_VITC_Q. Reserved. VDP_CCAPD_CLR. Reserved. VDP_CGMS_WSS_CHNGD_CLR. Reserved. VDP_GS_VPS_PDC_UTC_CHNG_CLR. 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 Reserved. VDP_VITC_MSKB. Reserved. VDP_TTXT_TYPE_MAN[1:0]. 0 00 01 10 PAL: Teletext-ITU-BT.653-625/50-A NTSC: Reserved PAL: Teletext-ITU-BT.653-625/50-B (WST) NTSC: Teletext-ITU-BT.653-525/60-B PAL: Teletext-ITU-BT.653-625/50-C NTSC: Teletext-ITU-BT.653-525/60-C OR EIA516 (NABTS) PAL: Teletext-ITU-BT.653-625/50-D NTSC: Teletext-ITU-BT.653-525/60-D User programming of teletext type disabled User programming of teletext type enabled Enable hamming decoding of WST packets Disable hamming decoding of WST packets 0 0 1 Masks VDP_VITC_Q Unmasks VDP_VITC_Q Masks VDP_GS_VPS_PDC_UTC_ CHNG_Q Unmasks VDP_GS_VPS_PDC_UTC_ CHNG_Q Masks VDP_CGMS_WSS_CHNGD_Q Unmasks VDP_CGMS_WSS_ CHNGD_Q Masks VDP_CCAPD_Q Unmasks VDP_CCAPD_Q Note that an interrupt in Register 0x4E for the CCAP, Gemstar, CGMS, WSS, VPS, PDC, UTC, and VITC data is using the VDP data slicer Do not clear Clears VDP_VITC_Q Do not clear Clears VDP_GS_VPS_PDC_UTC_ CHNG_Q x 0 1 0 0 1 Do not clear Clears VDP_CGMS_WSS_CHNGD_Q Do not clear Clears VDP_CCAPD_Q Note that an interrupt in Register 0x4E for the CCAP, Gemstar, CGMS, WSS, VPS, PDC, UTC, and VITC data is using the VDP data slicer 76543210 0 1 x 0 1 x 0 1 Gemstar/PDC/VPS/UTC data is not changed/available Gemstar/PDC/VPS/UTC data is changed/available CGMS/WSS data is not changed/not available CGMS/WSS data is changed/available Comments Closed captioning not detected Closed captioning detected Notes These bits can be cleared and masked by Register 0x4F and Register 0x50, respectively Note that an interrupt in Register 0x4E for the CCAP, Gemstar, CGMS, WSS, VPS, PDC, UTC, and VITC data is using the VDP data slicer
x 0 1 VITC data is not available in the VDP VITC data is available in the VDP
0x4F
Interrupt Clear 4 (Write Only)
Reserved. VDP_VITC_CLR. Reserved. VDP_CCAPD_MSKB. Reserved. VDP_CGMS_WSS_CHNGD_MSKB.
0x50
Interrupt Mask 4
Reserved. VDP_GS_VPS_PDC_UTC_CHNG_MSKB.
0x60
VDP_Config_1
11 VDP_TTXT_TYPE_MAN_ENABLE. 0 1 WST_PKT_DECODE_DISABLE. 0 1 Reserved. 1000
Rev. A | Page 101 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x61 VDP_Config_2
Default State)
Bit Description Reserved. AUTO_DETECT_GS_TYPE. Reserved. ADF_DID[4:0]. ADF_MODE[1:0]. 76543210 xx00 0 1 000 10101 00 01 10 11 ADF_ENABLE. 0 1 Comments Disable autodetection of Gemstar type Enable autodetection of Gemstar type User-specified DID sent in the ancillary data stream with VDP decoded data Nibble mode Byte mode, no code restrictions Byte mode with 0x00 and 0xFF prevented Reserved Disable insertion of VBI decoded data into ancillary 656 stream Enable insertion of VBI decoded data into ancillary 656 stream User-specified SDID sent in the ancillary data stream with VDP decoded data Ancillary data packet is spread across the Y and C data streams Ancillary data packet is duplicated on the Y and C data streams Sets VBI standard to be decoded from Line 318 (PAL); NTSC--N/A Decode default standards on the lines indicated in Table 65 Manually program the VBI standard to be decoded on each line; see Table 66 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Sets VBI standard to be decoded from Line 319 (PAL), Line 286 (NTSC) Sets VBI standard to be decoded from Line 6 (PAL), Line 23 (NTSC) Sets VBI standard to be decoded from Line 320 (PAL), Line 287 (NTSC) Sets VBI standard to be decoded from Line 7 (PAL), Line 24 (NTSC) Sets VBI standard to be decoded from Line 321 (PAL), Line 288 (NTSC) Sets VBI standard to be decoded from Line 8 (PAL), Line 25 (NTSC) Sets VBI standard to be decoded from Line 322 (PAL); NTSC--N/A Sets VBI standard to be decoded from Line 9 (PAL); NTSC--N/A Sets VBI standard to be decoded from Line 323 (PAL); NTSC--N/A Sets VBI standard to be decoded from Line 10 (PAL); NTSC--N/A Sets VBI standard to be decoded from Line 324 (PAL), Line272 (NTSC) Sets VBI standard to be decoded from Line 11 (PAL); NTSC--N/A Sets VBI standard to be decoded from Line 325 (PAL), Line 273(NTSC) Sets VBI standard to be decoded from Line 12 (PAL), Line 10 (NTSC) Sets VBI standard to be decoded from Line 326 (PAL), Line 274 (NTSC) Sets VBI standard to be decoded from Line 13 (PAL), Line 11 (NTSC) Sets VBI standard to be decoded from Line 327 (PAL), Line 275 (NTSC) Sets VBI standard to be decoded from Line 14 (PAL), Line 12 (NTSC) If set to 1, all VBI_DATA_ Px_Ny bits can be set as desired MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective Notes
0x62
VDP_ADF_Config_1
0x63
VDP_ADF_Config_2
ADF_SDID[5:0]. Reserved. DUPLICATE_ADF. x 0 1
101010
0x64
VDP_LINE_00E
VBI_DATA_P318[3:0]. Reserved. MAN_LINE_PGM. 000 0 1
0000
0x65
VDP_LINE_00F
VBI_DATA_P319_N286[3:0]. VBI_DATA_P6_N23[3:0].
0x66
VDP_LINE_010
VBI_DATA_P320_N287[3:0]. VBI_DATA_P7_N24[3:0].
0x67
VDP_LINE_011
VBI_DATA_P321_N288[3:0]. VBI_DATA_P8_N25[3:0].
0x68
VDP_LINE_012
VBI_DATA_P322[3:0]. VBI_DATA_P9[3:0].
0x69
VDP_LINE_013
VBI_DATA_P323[3:0]. VBI_DATA_P10[3:0].
0x6A
VDP_LINE_014
VBI_DATA_P324_N272[3:0]. VBI_DATA_P11[3:0].
0x6B
VDP_LINE_015
VBI_DATA_P325_N273[3:0]. VBI_DATA_P12_N10[3:0].
0x6C
VDP_LINE_016
VBI_DATA_P326_N274[3:0]. VBI_DATA_P13_N11[3:0].
0x6D
VDP_LINE_017
VBI_DATA_P327_N275[3:0]. VBI_DATA_P14_N12[3:0].
Rev. A | Page 102 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x6E VDP_LINE_018
Default State)
Bit Description VBI_DATA_P328_N276[3:0]. VBI_DATA_P15_N13[3:0]. 76543210 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Comments Sets VBI standard to be decoded from Line 328 (PAL), Line 276 (NTSC) Sets VBI standard to be decoded from Line 15 (PAL), Line 13 (NTSC) Sets VBI standard to be decoded from Line 329 (PAL), Line 277 (NTSC) Sets VBI standard to be decoded from Line 16 (PAL), Line14 (NTSC) Sets VBI standard to be decoded from Line 330 (PAL), Line 278 (NTSC) Sets VBI standard to be decoded from Line 17 (PAL), Line 15 (NTSC) Sets VBI standard to be decoded from Line 331 (PAL), Line 279 (NTSC) Sets VBI standard to be decoded from Line 18 (PAL), Line 16 (NTSC) Sets VBI standard to be decoded from Line 332 (PAL), Line 280 (NTSC) Sets VBI standard to be decoded from Line 19 (PAL), Line 17 (NTSC) Sets VBI standard to be decoded from Line 333 (PAL), Line 281 (NTSC) Sets VBI standard to be decoded from Line 20 (PAL), Line 18 (NTSC) Sets VBI standard to be decoded from Line 334 (PAL), Line 282 (NTSC) Sets VBI standard to be decoded from Line 21 (PAL), Line 19 (NTSC) Sets VBI standard to be decoded from Line 335 (PAL), Line 283 (NTSC) Sets VBI standard to be decoded from Line 22 (PAL), Line 20 (NTSC) Sets VBI standard to be decoded from Line 336 (PAL), Line 284 (NTSC) Sets VBI standard to be decoded from Line 23 (PAL), Line 21 (NTSC) Sets VBI standard to be decoded from Line 337 (PAL), Line 285 (NTSC) Sets VBI standard to be decoded from Line 24 (PAL), Line 22 (NTSC) Notes MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective
0x6F
VDP_LINE_019
VBI_DATA_P329_N277[3:0]. VBI_DATA_P16_N14[3:0].
0x70
VDP_LINE_01A
VBI_DATA_P330_N278[3:0]. VBI_DATA_P17_N15[3:0].
0x71
VDP_LINE_01B
VBI_DATA_P331_N279[3:0]. VBI_DATA_P18_N16[3:0].
0x72
VDP_LINE_01C
VBI_DATA_P332_N280[3:0]. VBI_DATA_P19_N17[3:0].
0x73
VDP_LINE_01D
VBI_DATA_P333_N281[3:0]. VBI_DATA_P20_N18[3:0].
0x74
VDP_LINE_01E
VBI_DATA_P334_N282[3:0]. VBI_DATA_P21_N19[3:0].
0x75
VDP_LINE_01F
VBI_DATA_P335_N283[3:0]. VBI_DATA_P22_N20[3:0].
0x76
VDP_LINE_020
VBI_DATA_P336_N284[3:0]. VBI_DATA_P23_N21[3:0].
0x77
VDP_LINE_021
VBI_DATA_P337_N285[3:0]. VBI_DATA_P24_N22[3:0].
Rev. A | Page 103 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x78 VDP_STATUS (Read Only)
Default State)
Bit Description CC_AVL. CC_EVEN_FIELD. 76543210 0 1 0 1 CGMS_WSS_AVL. Reserved. GS_PDC_VPS_UTC_AVL. 0 0 1 0 1 0 1 0 1 0 1 0 0 1 Reserved. GS_PDC_VPS_UTC_CLEAR. 0 0 1 Reserved. VITC_CLEAR. Reserved. CCAP_BYTE_1[7:0]. CCAP_BYTE_2[7:0]. CGMS_CRC[5:2]. Reserved. CGMS_WSS[13:8]. CGMS_CRC[1:0]. CGMS_WSS[7:0]. GS_VPS_PDC_UTC_BYTE_0[7:0]. GS_VPS_PDC_UTC_BYTE_1[7:0]. GS_VPS_PDC_UTC_BYTE_2[7:0]. GS_VPS_PDC_UTC_BYTE_3[7:0]. VPS_PDC_UTC_BYTE_4[7:0]. VPS_PDC_UTC_BYTE_5[7:0]. VPS_PDC_UTC_BYTE_6[7:0]. VPS_PDC_UTC_BYTE_7[7:0]. VPS_PDC_UTC_BYTE_8[7:0]. VPS_PDC_UTC_BYTE_9[7:0]. VPS_PDC_UTC_BYTE_10[7:0]. 0 0 1 0 xxxxxxxx xxxxxxxx xxxx 0000 xxxxxx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Does not reinitialize the VITC registers Reinitializes the VITC readback registers Decoded Byte 1 of CCAP Decoded Byte 2 of CCAP Decoded CRC sequence for CGMS Decoded CGMS/WSS data Decoded CRC sequence for CGMS Decoded CGMS/WSS data Decoded Gemstar/VPS/PDC/UTC data Decoded Gemstar/VPS/PDC/UTC data Decoded Gemstar/VPS/PDC/UTC data Decoded Gemstar/VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data This is a self-clearing bit Does not reinitialize the GS/PDC/VPS/ UTC registers Refreshes the GS/PDC/VPS/UTC readback registers This is a self-clearing bit Does not reinitialize the CGMS/WSS registers Reinitializes the CGMS/WSS readback registers This is a self-clearing bit VPS not detected VPS detected GS_PDC_VPS_UTC_CLEAR resets the GS_PDC_VPS_UTC_AVL bit 0 1 Comments Closed captioning not detected Closed captioning detected Closed captioning decoded from odd field Closed captioning decoded from even field CGMS/WSS not detected CGMS/WSS detected Notes CC_CLEAR resets the CC_AVL bit
CGMS_WSS_CLEAR resets the CGMS_WSS_AVL bit
GS_DATA_TYPE. VITC_AVL. TTXT_AVL. VDP_STATUS_CLEAR (Write Only) CC_CLEAR. Reserved. CGMS_WSS_CLEAR.
Gemstar_1x detected Gemstar_2x detected VITC not detected VITC_CLEAR resets the VITC_AVL bit VITC detected Teletext not detected Teletext detected Does not reinitialize the CCAP registers This is a self-clearing bit Reinitializes the CCAP readback registers
0x79 0x7A 0x7D 0x7E 0x7F 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E
VDP_CCAP_DATA_0 (Read Only) VDP_CCAP_DATA_1 (Read Only) VDP_CGMS_WSS_DATA_0 (Read Only) VDP_CGMS_WSS_DATA_1 (Read Only) VDP_CGMS_WSS_DATA_2 (Read Only) VDP_GS_VPS_PDC_UTC_0 (Read Only) VDP_GS_VPS_PDC_UTC_1 (Read Only) VDP_GS_VPS_PDC_UTC_2 (Read Only) VDP_GS_VPS_PDC_UTC_3 (Read Only) VDP_VPS_PDC_UTC_4 (Read Only) VDP_VPS_PDC_UTC_5 (Read Only) VDP_VPS_PDC_UTC_6 (Read Only) VDP_VPS_PDC_UTC_7 (Read only) VDP_VPS_PDC_UTC_8 (Read Only) VDP_VPS_PDC_UTC_9 (Read Only) VDP_VPS_PDC_UTC_10 (Read Only)
Rev. A | Page 104 of 112
ADV7180
Bit (Shading Indicates User Sub Map Address Register 0x8F VDP_VPS_PDC_UTC_11 (Read Only) 0x90 VDP_VPS_PDC_UTC_12 (Read Only) 0x92 VDP_VITC_DATA_0 (Read Only) 0x93 VDP_VITC_DATA_1 (Read Only) 0x94 VDP_VITC_DATA_2 (Read Only) 0x95 VDP_VITC_DATA_3 (Read only) 0x96 VDP_VITC_DATA_4 (Read Only) 0x97 VDP_VITC_DATA_5 (Read Only) 0x98 VDP_VITC_DATA_6 (Read Only) 0x99 VDP_VITC_DATA_7 (Read Only) 0x9A VDP_VITC_DATA_8 (Read Only) 0x9B VDP_VITC_CALC_CRC (Read Only) 0x9C VDP_OUTPUT_SEL
Default State)
Bit Description VPS_PDC_UTC_BYTE_11[7:0]. VPS_PDC_UTC_BYTE_12[7:0]. VITC_DATA_0[7:0]. VITC_DATA_1[7:0]. VITC_DATA_2[7:0]. VITC_DATA_3[7:0]. VITC_DATA_4[7:0]. VITC_DATA_5[7:0]. VITC_DATA_6[7:0]. VITC_DATA_7[7:0]. VITC_DATA_8[7:0]. VITC_CRC[7:0]. Reserved. WSS_CGMS_CB_CHANGE. 76543210 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0000 0 1 GS_VPS_PDC_UTC_CB_CHANGE. 0 1 I2C_GS_VPS_PDC_UTC[1:0]. 0 0 1 1 0 1 0 1 Disable content-based updating of CGMS and WSS data Enable content-based updating of CGMS and WSS data Disable content-based updating of Gemstar, VPS, PDC, and UTC data Enable content-based updating of Gemstar, VPS, PDC, and UTC data Gemstar_1x/Gemstar_2x VPS PDC UTC The AVAILABLE bit shows the availability of data only when its content has changed Comments Decoded VPS/PDC/UTC data Decoded VPS/PDC/UTC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC data Decoded VITC CRC data Notes
Standard expected to be decoded
Rev. A | Page 105 of 112
ADV7180 I2C PROGRAMMING EXAMPLES
ADV7180 LQFP-64
Mode 1 CVBS Input (Composite Video on AIN2)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
Table 105. Mode 1 CVBS Input
Register Address (Hex) 00 04 17 31 3D 3E 3F 0E 55 0E Register Value (Hex) 01 57 41 02 A2 6A A0 80 81 00 Notes INSEL = CVBS in on AIN2 Enable SFL Select SH1 Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window, color kill threshold to 2 BLM optimization BGB optimization Hidden space ADC configuration User space
Mode 2 S-Video Input (Y on AIN3 and C on AIN6)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 106. Mode 2 S-Video Input
Register Address (Hex) 00 04 31 3D 3E 3F 58 0E 55 0E Register Value (Hex) 08 57 02 A2 6A A0 04 80 81 00 Notes Insel = Y/C, Y = AIN3, C = AIN6 Enable SFL Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window, color kill threshold to 2 BLM optimization BGB optimization Mandatory write. This must be performed for correct operation. Hidden space ADC configuration User space
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN4, and Pb on AIN5)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8.
Table 107. Mode 3 YPrPb Input
Register Address (Hex) 00 31 3D 3E 3F 0E 55 0E Register Value (Hex) 09 02 A2 6A A0 80 81 00 Notes INSEL = YPrPb, Y = AIN1, Pr = AIN4, Pb = AIN5 Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window BLM optimization ADI recommended Hidden space ADC configuration User space
Rev. A | Page 106 of 112
ADV7180
ADV7180 LFCSP-40
Mode 1 CVBS Input (Composite Video on AIN1)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P0 to P7
Table 108. Mode 1 CVBS Input
Register Address (Hex) 00 04 17 31 3D 3E 3F 0E 55 0E Register Value (Hex) 00 57 41 02 A2 6A A0 80 81 00 Notes INSEL = CVBS in on AIN1 Enable SFL Select SH1 Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window, color kill threshold to 2 BLM optimization BGB optimization Hidden space ADC configuration User space
Mode 2 S-Video Input (Y on AIN1 and C on AIN2)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P0 to P7.
Table 109. Mode 2 S-Video Input
Register Address (Hex) 00 04 31 3D 3E 3F 58 0E 55 0E Register Value (Hex) 06 57 02 A2 6A A0 04 80 81 00 Notes Insel = Y/C, Y = AIN1, C = AIN2 Enable SFL Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window, color kill threshold to 2 BLM optimization BGB optimization Mandatory write. This must be performed for correct operation. Hidden space ADC configuration User space
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pb on AIN2, and Pr on AIN3)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P0 to P7.
Table 110. Mode 3 YPrPb Input
Register Address (Hex) 00 31 3D 3E 3F 0E 55 0E Register Value (Hex) 09 02 A2 6A A0 80 81 00 Notes INSEL = YPrPb, Y = AIN1, Pb = AIN2, Pr = AIN3 Clear NEWAV_MODE, SAV/EAV to suit ADV video encoders MWE enable manual window BLM optimization ADI recommended Hidden space ADC configuration User space
Rev. A | Page 107 of 112
ADV7180 PCB LAYOUT RECOMMENDATIONS
The ADV7180 is a high precision, high speed, mixed-signal device. To achieve the maximum performance from the part, it is important to have a well laid out PCB. The following is a guide for designing a board using the ADV7180. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. When using separate ground planes is unavoidable, placing a single ground plane under the ADV7180 is recommended. The location of the split should be under the ADV7180. In this case, it is even more important to place components wisely because the current loops are much longer, and current takes the path of least resistance. An example of a current loop is a power plane to the ADV7180 to the digital output trace to the digital data receiver to the digital ground plane to the analog ground plane.
ANALOG INTERFACE INPUTS
Care should be taken when routing the inputs on the PCB. Track lengths should be kept to a minimum, and 75 trace impedances should be used when possible. In addition, trace impedances other than 75 increase the chance of reflections.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with 0.1 F and 10 nF capacitors. The fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. Also avoid placing the capacitor on the opposite side of the PCB from the ADV7180, because doing so interposes resistive vias in the path. The decoupling capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor and then to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the 100 nF capacitor pads, down to the power plane, is generally the best approach (see Figure 51).
VDD 10nF GND 100nF VIA TO GND
05700-046
PLL
Place the PLL loop filter components as close as possible to the ELPF pin. It should also be placed on the same side of the PCB as the ADV7180. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with tolerances of 10% or less.
VREFN AND VREFP
The circuit associated with these pins should be placed as close as possible and on the same side of the PCB as the ADV7180.
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, requiring more current and in turn causing more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a 30 to 50 series resistor can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7180. If series resistors are used, place them as close as possible to the ADV7180 pins. However, try not to add vias or extra length to the output trace to make the resistors closer. If possible, limit the capacitance that each of the digital outputs drives to less than 15 pF. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7180, creating more digital noise on its power supplies. The ADV7180 LFCSP-40 has an exposed metal paddle on the bottom of the LFCSP package. This paddle must be soldered to PCB ground for proper heat dissipation and also for noise and mechanical strength benefits.
VIA TO SUPPLY
Figure 51. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good stability of PVDD. Careful attention must be paid to regulation, filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (AVDD, DVDD, DVDDIO, and PVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVDD, from a different, cleaner power source, for example, from a 12 V supply. Using a single ground plane for the entire board is also recommended. This ground plane should have a space between the analog and digital sections of the PCB (see Figure 52).
ADV7180
05700-047
DIGITAL INPUTS
The digital inputs on the ADV7180 are designed to work with 3.3 V signals and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder.
ANALOG SECTION
DIGITAL SECTION
Figure 52. PCB Ground Layout
Rev. A | Page 108 of 112
ADV7180 TYPICAL CIRCUIT CONNECTION
Examples of how to connect the ADV7180 LQFP-64 and ADV7180 LFCSP-40 video decoder are shown in Figure 53 and Figure 54. For a detailed schematic diagram for the ADV7180 evaluation boards, contact local Analog Devices field applications engineers or local Analog Devices distributor.
ANALOG_INPUT_1 36 0.1F AIN1 39 0.1F 10nF 0.1F 10nF 0.1F 10nF 0.1F 10nF DVDD_1.8V DVDDIO AVDD_1.8V
ANALOG_INPUT_2 36
0.1F AIN2 39 DVDDIO _3.3V DVDD _1.8V AVDD_1.8V PVDD_1.8V 0.1F
10nF
ANALOG_INPUT_3 36
0.1F
27 36
AIN3 39 AIN1 AIN2 AIN3 RESET 23 29 30 31 AIN1 AIN2 AIN3
14
1
4
20
P[0:7]
DVDD
DVDDIO
DVDDIO
DVDD
PVDD
AVDD
RESET
KEEP C14 AND C15 AS CLOSE AS POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE OF THE PCB AS THE ADV7180. 26 0.1F 0.1F 25 0.1F VREFP VREFN
ADV7180BCPZ
LFCSP-40
P0 P1 P2 P3 P4 P5 P6 P7
17 16 10 9 8 7 6 5
P0 P1 P2 P3 P4 P5 P6 P7
YCrCb 8-BIT 656 DATA
LLC LOCATE CLOSE TO, AND ON THE SAME SIDE AS, THE ADV7180. 13 47pF 28.63636MHz * 1M 12 47pF XTAL1 XTAL INTRQ SFL VS/FIELD HS
11 38 2 37 39
LLC INTRQ SFL VS/FIELD HS
DVDDIO 4k ALSB TIED HI I2C ADDRESS = 42h ALSB TIED LOW I2C ADDRESS = 40h 32 ALSB EXTERNAL LOOP FILTER 19 10nF PVDD_1.8V
POWER_DOWN SCLK SDA
18 34 33
PWRDWN SCLK
DGND DGND DGND DGND
ELPF
82nF
TEST_0 AGND AGND AGND
1.69k KEEP CLOSE TO THE ADV7180 AND ON THE SAME SIDE OF PCB AS THE ADV7180.
SDATA
40 3 15 35
28 21 24
Figure 53. ADV7180 LFCSP-40 Typical Connection Diagram
Rev. A | Page 109 of 112
05700-048
*REFER TO ANALOG DEVICES CRYSTAL APPLICATION NOTE FOR PROPER CAPACITOR LOADING.
22
ADV7180
ANALOG_INPUT_1 Y 36 ANALOG_INPUT_2 CVBS 36 ANALOG_INPUT_3 YC_Y 36 ANALOG_INPUT_4 Cr 36 ANALOG_INPUT_5 Cb 36 ANALOG_INPUT_6 YC_C 36 0.1F AIN1 39 DVDD _1.8V 0.1F AIN2 39 DVDDIO _3.3V 0.1F AIN3 39 0.1F 10nF DVDDIO _3.3V 10nF 0.1F PVDD_1.8V 0.1F 10nF AVDD _1.8V 0.1F 10nF DVDD _1.8V 0.1F
THE SUGGESTED INPUT ARRANGEMENT IS AS SEEN ON THE EVAL BOARD AND IS DIRECTLY SUPPORTED BY INSEL.
10nF
0.1F AIN4 39
0.1F
10nF P[0:7]
8-BIT OUTPUT MODE --656/601 YCbCr 16-BIT OUTPUT MODE Y CbCr
23
58
40 AVDD
DVDD
DVDDIO
0.1F AIN5 39 AIN1 AIN2 AIN3 AIN6 39 AIN4 AIN5 AIN6 KEEP VREFN AND VREFP CAPS AS CLOSE AS POSSIBLE TO THE ADV7180 AND ON THE SAME SIDE OF THE PCB AS THE ADV7180.
35 36 46 47 48 49
DVDDIO
DVDD
PVDD
31
11
4
AIN1 AIN2 AIN3 AIN4 AIN5 AIN6
0.1F
ADV7180BSTZ
LQFP-64
P0 P1 P2 P3 P4 P5 P6 P7
26 25 19 18 17 16 15 14 8 7 6 5 62 61 60 59 1 55 56 12 13 63 64 2 9
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 INT GPO3 GPO2 GPO1 GPO0 FIELD
DATA BUS P[0:7] P[8:15]
P[8:15]
39 0.1F 0.1F 38 0.1F DO NOT STUFF C19
VREFN
P8 P9 P10 P11 P12 P13 P14 P15 INTRQ
VREFP
22 47pF 28.63636MHz * 1M 21 47pF 51 29
XTAL
GPO3 GPO2 GPO1 GPO0 FIELD VS
VSYNC HS SFL EXTERNAL LOOP FILTER 10nF PVDD _1.8V
XTAL1
HS SFL
RESET POWER_DOWN DVDDIO _3.3V 4k TIE HI: I2C ADDRESS = 42 TIE LOW: I2C ADDRESS = 40 SCLK SDA 33
RESET PWRDWN
NC ELPF
27, 28, 33, 41, 42, 44, 45, 50 30
82nF 52 ALSB 1.69k KEEP CLOSE TO THE ADV7180 AND ON THE SAME SIDE OF PCB AS THE ADV7180. 54 53 33 LLC SDATA
AGND AGND AGND TEST_0
20
LLC
SCLK
DGND DGND DGND DGND 3 10 24 57
NC = NO CONNECT
Figure 54. ADV7180 LQFP-64 Typical Connection Diagram
Rev. A | Page 110 of 112
05700-049
*REFER TO ANALOG DEVICES CRYSTAL APPLICATION NOTE FOR PROPER CAPACITOR LOADING.
32 37 43 34
ADV7180 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
EXPOSED PADDLE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION, NOISE IMMUNITY AND MECHANICAL STRENGTH BENEFITS.
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters
12.20 12.00 SQ 11.80
64 1 PIN 1 49 48
0.75 0.60 0.45
1.60 MAX
TOP VIEW
(PINS DOWN)
10.20 10.00 SQ 9.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0
0.08 COPLANARITY
16 17 32
33
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 56. 64-Lead Low Profile Quad Flat Package [LQFP] 10 mm x 10 mm Body (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADV7180BCPZ 1 ADV7180BSTZ1 EVAL-ADV7180LQEB EVAL-ADV7180LFEB
1
Temperature Range -40C to +85C -40C to +85C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the LQFP Evaluation Board for LFCSP
Z = Pb-free part.
Note: The ADV7180 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering at up to 255C (5C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C.
Rev. A | Page 111 of 112
051706-A
ROTATED 90 CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
Package Option CP-40 ST-64-2
ADV7180 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05700-0-11/06(A)
Rev. A | Page 112 of 112

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